An N/M-Ratio All-Digital Clock Generator with a Pseudo-NMOS Comparator-Based Programmable Divider

An N/M-Ratio All-Digital Clock Generator with a Pseudo-NMOS Comparator-Based Programmable Divider

A multiplying delay-locked loop (MDLL)-based all-digital clock generator with a programmable N/M-ratio frequency multiplication capability for digital SoC is presented. The proposed digital MDLL provides programmable N/M-ratio frequency multiplication using a new high-speed Pseudo-NMOS comparator-ba...

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Bibliographic Details
Main Author: Jongsun Kim
Format: Article
Language:English
Published: MDPI AG 2022-01-01
Series:Electronics
Subjects:
clock generator
multiplying delay-locked loop
MDLL
frequency divider
SoC
Online Access:https://www.mdpi.com/2079-9292/11/2/261

Internet

https://www.mdpi.com/2079-9292/11/2/261

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