A power-efficient pipeline based clock gating FIFO for a dual ported memory array
A FIFO is a special type of buffer that controls the data flow between the sender and receiver. It is used to monitor the serial data flow and to avoid mismatch conditions. In general, the dual-ported memory cell array suffers from dynamic power dissipation. In this research article, a 128 x 128-b...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Prince of Songkla University
2023-04-01
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| Series: | Songklanakarin Journal of Science and Technology (SJST) |
| Subjects: | |
| Online Access: | https://sjst.psu.ac.th/journal/45-2/3.pdf |