Design of 10T SRAM cell with improved read performance and expanded write margin

Design of 10T SRAM cell with improved read performance and expanded write margin

Abstract The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes. The impact of variability of process, temperature and voltage, on different performance parameters t...

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Bibliographic Details
Main Authors: Ashish Sachdeva, V. K. Tomar
Format: Article
Language:English
Published: Hindawi-IET 2021-01-01
Series:IET Circuits, Devices and Systems
Subjects:
CMOS memory circuits
electronic engineering computing
integrated circuit design
low‐power electronics
network topology
SRAM chips
Online Access:https://doi.org/10.1049/cds2.12006

Internet

https://doi.org/10.1049/cds2.12006

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