Design of 10T SRAM cell with improved read performance and expanded write margin
Abstract The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes. The impact of variability of process, temperature and voltage, on different performance parameters t...
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| Format: | Article |
| Language: | English |
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Hindawi-IET
2021-01-01
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| Series: | IET Circuits, Devices and Systems |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/cds2.12006 |
| _version_ | 1797430613533261824 |
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| author | Ashish Sachdeva V. K. Tomar |
| author_facet | Ashish Sachdeva V. K. Tomar |
| author_sort | Ashish Sachdeva |
| collection | DOAJ |
| description | Abstract The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes. The impact of variability of process, temperature and voltage, on different performance parameters turns out to be most relevant issues in the nanometre SRAM design. The authors propose a 10T SRAM circuit that shows reduction in read power dissipation while maintaining fair performance and stability. Impression of process parameter variations on various design metrics such as read power, read current and data retention voltage of the proposed cell are presented and compared with already proposed SRAM cell. The projected topology offers differential read and single‐ended write operation. The read margin and write margin are enhanced by 8.69% and 16.85% respectively in comparison to standard 6T SRAM cell even when single‐ended write operation is performed. Furthermore, the read and write delay of projected topology improve by 1.78× and 2.326× in comparison with conventional 6T bit SRAM cell. In FF process corner, the proposed topology shows lowest data retention voltage (DRV) and minimum variation in DRV with temperature. Out of all considered topologies, the proposed circuit is optimized to minimum power delay product during read operation. Further, standby power and read power of proposed 10T cell is reduced by 34.65% and 2.03× in contrast to conventional 6T SRAM at 0.9 V supply voltage. Analysis of process variations tolerance read power and read current is also presented with 45 nm generic process design kit technology file using cadence virtuoso tool. |
| first_indexed | 2024-03-09T09:30:08Z |
| format | Article |
| id | doaj.art-89c3b594cf4c469d96fc8de6a893508d |
| institution | Directory Open Access Journal |
| issn | 1751-858X 1751-8598 |
| language | English |
| last_indexed | 2024-03-09T09:30:08Z |
| publishDate | 2021-01-01 |
| publisher | Hindawi-IET |
| record_format | Article |
| series | IET Circuits, Devices and Systems |
| spelling | doaj.art-89c3b594cf4c469d96fc8de6a893508d2023-12-02T04:08:53ZengHindawi-IETIET Circuits, Devices and Systems1751-858X1751-85982021-01-01151426410.1049/cds2.12006Design of 10T SRAM cell with improved read performance and expanded write marginAshish Sachdeva0V. K. Tomar1ECE Department GLA University Mathura Uttar Pradesh281406 IndiaECE Department GLA University Mathura Uttar Pradesh281406 IndiaAbstract The need of genuine processors operation improvement cultivates the necessity for reliable, low power and fast memories. Several challenges follow this improvement at lower technology nodes. The impact of variability of process, temperature and voltage, on different performance parameters turns out to be most relevant issues in the nanometre SRAM design. The authors propose a 10T SRAM circuit that shows reduction in read power dissipation while maintaining fair performance and stability. Impression of process parameter variations on various design metrics such as read power, read current and data retention voltage of the proposed cell are presented and compared with already proposed SRAM cell. The projected topology offers differential read and single‐ended write operation. The read margin and write margin are enhanced by 8.69% and 16.85% respectively in comparison to standard 6T SRAM cell even when single‐ended write operation is performed. Furthermore, the read and write delay of projected topology improve by 1.78× and 2.326× in comparison with conventional 6T bit SRAM cell. In FF process corner, the proposed topology shows lowest data retention voltage (DRV) and minimum variation in DRV with temperature. Out of all considered topologies, the proposed circuit is optimized to minimum power delay product during read operation. Further, standby power and read power of proposed 10T cell is reduced by 34.65% and 2.03× in contrast to conventional 6T SRAM at 0.9 V supply voltage. Analysis of process variations tolerance read power and read current is also presented with 45 nm generic process design kit technology file using cadence virtuoso tool.https://doi.org/10.1049/cds2.12006CMOS memory circuitselectronic engineering computingintegrated circuit designlow‐power electronicsnetwork topologySRAM chips |
| spellingShingle | Ashish Sachdeva V. K. Tomar Design of 10T SRAM cell with improved read performance and expanded write margin IET Circuits, Devices and Systems CMOS memory circuits electronic engineering computing integrated circuit design low‐power electronics network topology SRAM chips |
| title | Design of 10T SRAM cell with improved read performance and expanded write margin |
| title_full | Design of 10T SRAM cell with improved read performance and expanded write margin |
| title_fullStr | Design of 10T SRAM cell with improved read performance and expanded write margin |
| title_full_unstemmed | Design of 10T SRAM cell with improved read performance and expanded write margin |
| title_short | Design of 10T SRAM cell with improved read performance and expanded write margin |
| title_sort | design of 10t sram cell with improved read performance and expanded write margin |
| topic | CMOS memory circuits electronic engineering computing integrated circuit design low‐power electronics network topology SRAM chips |
| url | https://doi.org/10.1049/cds2.12006 |
| work_keys_str_mv | AT ashishsachdeva designof10tsramcellwithimprovedreadperformanceandexpandedwritemargin AT vktomar designof10tsramcellwithimprovedreadperformanceandexpandedwritemargin |