120V Low Side LDMOS Device with Sided Isolation of 0.35μm CMOS Compatible Process

120V Low Side LDMOS Device with Sided Isolation of 0.35μm CMOS Compatible Process

In this paper, a novel 120V multiple RESURF lateral double-diffused MOS (LDMOS) transistor with shallow trench isolation (STI) structure in low side is developed and successfully simulated. The proposed multiple RESURF LDMOS is able to achieve better ESOA performance while maintaining a benchmark sp...

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Bibliographic Details
Main Authors: Deivasigamani Ravi, Sheu Gene, Aryadeep Chirag, Sai S. Krishna, Selvendran S., Yang Shao-Ming
Format: Article
Language:English
Published: EDP Sciences 2018-01-01
Series:MATEC Web of Conferences
Online Access:https://doi.org/10.1051/matecconf/201820102005

Internet

https://doi.org/10.1051/matecconf/201820102005

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