120V Low Side LDMOS Device with Sided Isolation of 0.35μm CMOS Compatible Process
In this paper, a novel 120V multiple RESURF lateral double-diffused MOS (LDMOS) transistor with shallow trench isolation (STI) structure in low side is developed and successfully simulated. The proposed multiple RESURF LDMOS is able to achieve better ESOA performance while maintaining a benchmark sp...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
EDP Sciences
2018-01-01
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| Series: | MATEC Web of Conferences |
| Online Access: | https://doi.org/10.1051/matecconf/201820102005 |
| _version_ | 1819133076716912640 |
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| author | Deivasigamani Ravi Sheu Gene Aryadeep Chirag Sai S. Krishna Selvendran S. Yang Shao-Ming |
| author_facet | Deivasigamani Ravi Sheu Gene Aryadeep Chirag Sai S. Krishna Selvendran S. Yang Shao-Ming |
| author_sort | Deivasigamani Ravi |
| collection | DOAJ |
| description | In this paper, a novel 120V multiple RESURF lateral double-diffused MOS (LDMOS) transistor with shallow trench isolation (STI) structure in low side is developed and successfully simulated. The proposed multiple RESURF LDMOS is able to achieve better ESOA performance while maintaining a benchmark specific on-resistance with breakdown voltage over 120 Volts. The key feature of this novel device is linear p-top rings which are located in the n-drift region. Optimization of p-top mask design and n-drift region concentration is performed in order to achieve the lowest on-resistance possible with the desired breakdown voltage. |
| first_indexed | 2024-12-22T09:41:33Z |
| format | Article |
| id | doaj.art-8dc0bd3c66544392af76d2e540a6186c |
| institution | Directory Open Access Journal |
| issn | 2261-236X |
| language | English |
| last_indexed | 2024-12-22T09:41:33Z |
| publishDate | 2018-01-01 |
| publisher | EDP Sciences |
| record_format | Article |
| series | MATEC Web of Conferences |
| spelling | doaj.art-8dc0bd3c66544392af76d2e540a6186c2022-12-21T18:30:39ZengEDP SciencesMATEC Web of Conferences2261-236X2018-01-012010200510.1051/matecconf/201820102005matecconf_ici2017_02005120V Low Side LDMOS Device with Sided Isolation of 0.35μm CMOS Compatible ProcessDeivasigamani RaviSheu GeneAryadeep ChiragSai S. KrishnaSelvendran S.Yang Shao-MingIn this paper, a novel 120V multiple RESURF lateral double-diffused MOS (LDMOS) transistor with shallow trench isolation (STI) structure in low side is developed and successfully simulated. The proposed multiple RESURF LDMOS is able to achieve better ESOA performance while maintaining a benchmark specific on-resistance with breakdown voltage over 120 Volts. The key feature of this novel device is linear p-top rings which are located in the n-drift region. Optimization of p-top mask design and n-drift region concentration is performed in order to achieve the lowest on-resistance possible with the desired breakdown voltage.https://doi.org/10.1051/matecconf/201820102005 |
| spellingShingle | Deivasigamani Ravi Sheu Gene Aryadeep Chirag Sai S. Krishna Selvendran S. Yang Shao-Ming 120V Low Side LDMOS Device with Sided Isolation of 0.35μm CMOS Compatible Process MATEC Web of Conferences |
| title | 120V Low Side LDMOS Device with Sided Isolation of 0.35μm CMOS Compatible Process |
| title_full | 120V Low Side LDMOS Device with Sided Isolation of 0.35μm CMOS Compatible Process |
| title_fullStr | 120V Low Side LDMOS Device with Sided Isolation of 0.35μm CMOS Compatible Process |
| title_full_unstemmed | 120V Low Side LDMOS Device with Sided Isolation of 0.35μm CMOS Compatible Process |
| title_short | 120V Low Side LDMOS Device with Sided Isolation of 0.35μm CMOS Compatible Process |
| title_sort | 120v low side ldmos device with sided isolation of 0 35μm cmos compatible process |
| url | https://doi.org/10.1051/matecconf/201820102005 |
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