Fixed-latency System for High-speed Serial Transmission Between FPGA Devices with Forward Error Correction

Fixed-latency System for High-speed Serial Transmission Between FPGA Devices with Forward Error Correction

This paper presents the design of a compact protocol for fixed-latency, high-speed, reliable, serial transmission between simple field-programmable gate arrays (FPGA) devices. Implementation of the project aims to delineate word boundaries, provide randomness to the electromagnetic interference (EMI...

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Bibliographic Details
Main Authors: Michał Kruszewski, Wojciech Marek Zabołotny
Format: Article
Language:English
Published: Polish Academy of Sciences 2020-09-01
Series:International Journal of Electronics and Telecommunications
Subjects:
data transmission
fixed-latency transmission
forward error correction
orthogonal concatenated coding
fpga
Online Access:https://journals.pan.pl/Content/117106/PDF/75_2563_Kruszewski_L_skl.pdf

Internet

https://journals.pan.pl/Content/117106/PDF/75_2563_Kruszewski_L_skl.pdf

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