Fixed-latency System for High-speed Serial Transmission Between FPGA Devices with Forward Error Correction
This paper presents the design of a compact protocol for fixed-latency, high-speed, reliable, serial transmission between simple field-programmable gate arrays (FPGA) devices. Implementation of the project aims to delineate word boundaries, provide randomness to the electromagnetic interference (EMI...
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| Format: | Article |
| Language: | English |
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Polish Academy of Sciences
2020-09-01
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| Series: | International Journal of Electronics and Telecommunications |
| Subjects: | |
| Online Access: | https://journals.pan.pl/Content/117106/PDF/75_2563_Kruszewski_L_skl.pdf |
| _version_ | 1811314339000352768 |
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| author | Michał Kruszewski Wojciech Marek Zabołotny |
| author_facet | Michał Kruszewski Wojciech Marek Zabołotny |
| author_sort | Michał Kruszewski |
| collection | DOAJ |
| description | This paper presents the design of a compact protocol for fixed-latency, high-speed, reliable, serial transmission between simple field-programmable gate arrays (FPGA) devices. Implementation of the project aims to delineate word boundaries, provide randomness to the electromagnetic interference (EMI) generated by the electrical transitions, allow for clock recovery and maintain direct current (DC) balance. An orthogonal concatenated coding scheme is used for correcting transmission errors using modified Bose–Chaudhuri–Hocquenghem (BCH) code capable of correcting all single bit errors and most of the double-adjacent errors. As a result all burst errors of a length up to 31 bits, and some of the longer group errors, are corrected within 256 bits long packet. The efficiency of the proposed solution equals 46.48%, as 119 out of 256 bits are fully available to the user. The design has been implemented and tested on Xilinx Kintex UltraScale+ KCU116 Evaluation Kit with a data rate of 28.2 Gbps. Sample latency analysis has also been performed so that user could easily carry out calculations for different transmission speed. The main advancement of the work is the use of modified BCH(15, 11) code that leads to high error correction capabilities for burst errors and user friendly packet length. |
| first_indexed | 2024-04-13T11:10:07Z |
| format | Article |
| id | doaj.art-8def7ee6ce504fdb9c931d244c0d6545 |
| institution | Directory Open Access Journal |
| issn | 2081-8491 2300-1933 |
| language | English |
| last_indexed | 2024-04-13T11:10:07Z |
| publishDate | 2020-09-01 |
| publisher | Polish Academy of Sciences |
| record_format | Article |
| series | International Journal of Electronics and Telecommunications |
| spelling | doaj.art-8def7ee6ce504fdb9c931d244c0d65452022-12-22T02:49:08ZengPolish Academy of SciencesInternational Journal of Electronics and Telecommunications2081-84912300-19332020-09-01vol. 66No 3545553https://doi.org/10.24425/ijet.2020.134011Fixed-latency System for High-speed Serial Transmission Between FPGA Devices with Forward Error CorrectionMichał KruszewskiWojciech Marek ZabołotnyThis paper presents the design of a compact protocol for fixed-latency, high-speed, reliable, serial transmission between simple field-programmable gate arrays (FPGA) devices. Implementation of the project aims to delineate word boundaries, provide randomness to the electromagnetic interference (EMI) generated by the electrical transitions, allow for clock recovery and maintain direct current (DC) balance. An orthogonal concatenated coding scheme is used for correcting transmission errors using modified Bose–Chaudhuri–Hocquenghem (BCH) code capable of correcting all single bit errors and most of the double-adjacent errors. As a result all burst errors of a length up to 31 bits, and some of the longer group errors, are corrected within 256 bits long packet. The efficiency of the proposed solution equals 46.48%, as 119 out of 256 bits are fully available to the user. The design has been implemented and tested on Xilinx Kintex UltraScale+ KCU116 Evaluation Kit with a data rate of 28.2 Gbps. Sample latency analysis has also been performed so that user could easily carry out calculations for different transmission speed. The main advancement of the work is the use of modified BCH(15, 11) code that leads to high error correction capabilities for burst errors and user friendly packet length.https://journals.pan.pl/Content/117106/PDF/75_2563_Kruszewski_L_skl.pdfdata transmissionfixed-latency transmissionforward error correctionorthogonal concatenated codingfpga |
| spellingShingle | Michał Kruszewski Wojciech Marek Zabołotny Fixed-latency System for High-speed Serial Transmission Between FPGA Devices with Forward Error Correction International Journal of Electronics and Telecommunications data transmission fixed-latency transmission forward error correction orthogonal concatenated coding fpga |
| title | Fixed-latency System for High-speed Serial Transmission Between FPGA Devices with Forward Error Correction |
| title_full | Fixed-latency System for High-speed Serial Transmission Between FPGA Devices with Forward Error Correction |
| title_fullStr | Fixed-latency System for High-speed Serial Transmission Between FPGA Devices with Forward Error Correction |
| title_full_unstemmed | Fixed-latency System for High-speed Serial Transmission Between FPGA Devices with Forward Error Correction |
| title_short | Fixed-latency System for High-speed Serial Transmission Between FPGA Devices with Forward Error Correction |
| title_sort | fixed latency system for high speed serial transmission between fpga devices with forward error correction |
| topic | data transmission fixed-latency transmission forward error correction orthogonal concatenated coding fpga |
| url | https://journals.pan.pl/Content/117106/PDF/75_2563_Kruszewski_L_skl.pdf |
| work_keys_str_mv | AT michałkruszewski fixedlatencysystemforhighspeedserialtransmissionbetweenfpgadeviceswithforwarderrorcorrection AT wojciechmarekzabołotny fixedlatencysystemforhighspeedserialtransmissionbetweenfpgadeviceswithforwarderrorcorrection |