Implementation of a low‐power LVQ architecture on FPGA

Implementation of a low‐power LVQ architecture on FPGA

This study presents an architecture‐optimising methodology for embedding an learning vector quantization (LVQ) neural network on an field programmable gate array (FPGA) device. The embedded architecture contains both learning and decision circuitry and is optimised towards the lowest power/energy co...

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Bibliographic Details
Main Authors: Najoua Chalbi, Mohamed Boubaker, Mohamed Hedi Bedoui
Format: Article
Language:English
Published: Hindawi-IET 2017-11-01
Series:IET Circuits, Devices and Systems
Subjects:
LVQ topology
analytical power model
Xpower tool
ergonomic utilisation
FPGA software design tools
low-power-energy architecture
Online Access:https://doi.org/10.1049/iet-cds.2016.0311

Internet

https://doi.org/10.1049/iet-cds.2016.0311

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