Enhancing the Hardware Pipelining Optimization Technique of the SHA-3 via FPGA

Enhancing the Hardware Pipelining Optimization Technique of the SHA-3 via FPGA

Information is transmitted between multiple insecure routing hops in text, image, video, and audio. Thus, this multi-hop digital data transfer makes secure transmission with confidentiality and integrity imperative. This protection of the transmitted data can be achieved via hashing algorithms. Furt...

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Bibliographic Details
Main Authors: Argyrios Sideris, Minas Dasygenis
Format: Article
Language:English
Published: MDPI AG 2023-08-01
Series:Computation
Subjects:
hardware accelerator
SHA-3
hardware optimization
cryptography
FPGA
round constant (RC) generator
Online Access:https://www.mdpi.com/2079-3197/11/8/152

Internet

https://www.mdpi.com/2079-3197/11/8/152

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