Using Codes of Output Collections for Hardware Reduction in Circuits of LUT-Based Finite State Machines
A method is proposed which aims to reduce the hardware in FPGA-based circuits of Mealy finite state machines (FSMs). The proposed method is a type of structural decomposition method. Its main goal is the reducing the number of look-up table (LUT) elements in FSM circuits compared to the three-block...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2022-06-01
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| Series: | Electronics |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2079-9292/11/13/2050 |