Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell

Tolerant and low power subtractor with 4:2 compressor and a new TG‐PTL‐float full adder cell

Abstract A new 1‐bit full adder (FA) cell illustrating low‐power, high‐speed, and a small area is presented by a combination of transmission gate (TG), pass transistor logic (PTL), and float techniques. Using the proposed cell, a 4:2 compressor is implemented and its performance is investigated unde...

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Bibliographic Details
Main Authors: Ayoub Sadeghi, Nabiollah Shiri, Mahmood Rafiee, Rahim Ghayour
Format: Article
Language:English
Published: Hindawi-IET 2022-09-01
Series:IET Circuits, Devices and Systems
Subjects:
compressor
difference detection
full adder
image processing
subtractor
Online Access:https://doi.org/10.1049/cds2.12117

Internet

https://doi.org/10.1049/cds2.12117

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