Trends and challenges in design of embedded BCH error correction codes in multi-levels NAND flash memory devices
Recently, there has been a growing concern regarding the dependability of NAND flash cells, notably as the scale of their features reduces. To address this issue, implementing error correction codes (ECC) proves to be an effective solution. Among the various methods, BCH coding has gained significan...
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| Format: | Article |
| Language: | English |
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Elsevier
2024-04-01
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| Series: | Memories - Materials, Devices, Circuits and Systems |
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| Online Access: | http://www.sciencedirect.com/science/article/pii/S277306462400001X |
| _version_ | 1827313611126603776 |
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| author | Saeideh Nabipour Javad Javidan Rolf Drechsler |
| author_facet | Saeideh Nabipour Javad Javidan Rolf Drechsler |
| author_sort | Saeideh Nabipour |
| collection | DOAJ |
| description | Recently, there has been a growing concern regarding the dependability of NAND flash cells, notably as the scale of their features reduces. To address this issue, implementing error correction codes (ECC) proves to be an effective solution. Among the various methods, BCH coding has gained significant interest because of its exceptional error correction capabilities. Over the last decades, there has been much research on BCH decoder design to meet the demand for reduced hardware complexities, minimized delay performance, and lower power dissipation to enable BCH decoders and their VLSI implementations to facilitate different code lengths and rates of code. This paper surveys the trends and challenges associated with BCH decoder in NAND flash memory devices, the possible solutions for overcoming of time and area overhead in architecture of BCH decoder block and an examination of the extent to which present architectures will respond to the escalating requirements on data transfer rate, bit error rate (BER) performance, power consumption, and silicon area that will be essential for the extensive acceptance of BCH code in applications that will emerge in the near future. To demonstrate the need for such solutions, we present rigorous experimental data on BCH error correction codes on various types of flash memory errors, to motivate the need for such techniques. Based on the understanding developed by the experimental characterization, we describe several area-delay efficient techniques, including three low-latency decoding strategies for implementing the BCH decoder: pipeline method, re-encoding scheme, and parallelization method, and various hardware optimization strategies for the BCH decoder, such as three area-efficient syndrome block architectures, four error locator polynomial detection algorithms, and four error position identification algorithms using the Chien search method. We investigate the increase in reliability that each of these methods brings. We also briefly address future directions that these methods and flash memory techniques could evolve into the future. |
| first_indexed | 2024-03-08T11:23:51Z |
| format | Article |
| id | doaj.art-92e537e2dfce4c9dacd2b5bb963f434a |
| institution | Directory Open Access Journal |
| issn | 2773-0646 |
| language | English |
| last_indexed | 2024-04-24T22:19:22Z |
| publishDate | 2024-04-01 |
| publisher | Elsevier |
| record_format | Article |
| series | Memories - Materials, Devices, Circuits and Systems |
| spelling | doaj.art-92e537e2dfce4c9dacd2b5bb963f434a2024-03-20T06:12:11ZengElsevierMemories - Materials, Devices, Circuits and Systems2773-06462024-04-017100099Trends and challenges in design of embedded BCH error correction codes in multi-levels NAND flash memory devicesSaeideh Nabipour0Javad Javidan1Rolf Drechsler2Institute of Computer Science, University of Bremen, Bremen, Germany; Corresponding author.Faculty of Electrical and Computer Engineering, University of Mohaghegh Ardabili, Ardabil, IranInstitute of Computer Science, University of Bremen, Bremen, Germany; Cyber-Physical Systems, DFKI GmbH, Bremen, GermanyRecently, there has been a growing concern regarding the dependability of NAND flash cells, notably as the scale of their features reduces. To address this issue, implementing error correction codes (ECC) proves to be an effective solution. Among the various methods, BCH coding has gained significant interest because of its exceptional error correction capabilities. Over the last decades, there has been much research on BCH decoder design to meet the demand for reduced hardware complexities, minimized delay performance, and lower power dissipation to enable BCH decoders and their VLSI implementations to facilitate different code lengths and rates of code. This paper surveys the trends and challenges associated with BCH decoder in NAND flash memory devices, the possible solutions for overcoming of time and area overhead in architecture of BCH decoder block and an examination of the extent to which present architectures will respond to the escalating requirements on data transfer rate, bit error rate (BER) performance, power consumption, and silicon area that will be essential for the extensive acceptance of BCH code in applications that will emerge in the near future. To demonstrate the need for such solutions, we present rigorous experimental data on BCH error correction codes on various types of flash memory errors, to motivate the need for such techniques. Based on the understanding developed by the experimental characterization, we describe several area-delay efficient techniques, including three low-latency decoding strategies for implementing the BCH decoder: pipeline method, re-encoding scheme, and parallelization method, and various hardware optimization strategies for the BCH decoder, such as three area-efficient syndrome block architectures, four error locator polynomial detection algorithms, and four error position identification algorithms using the Chien search method. We investigate the increase in reliability that each of these methods brings. We also briefly address future directions that these methods and flash memory techniques could evolve into the future.http://www.sciencedirect.com/science/article/pii/S277306462400001XNAND flash memoryBCH codesBCH decoderHardware complexityLow latency |
| spellingShingle | Saeideh Nabipour Javad Javidan Rolf Drechsler Trends and challenges in design of embedded BCH error correction codes in multi-levels NAND flash memory devices Memories - Materials, Devices, Circuits and Systems NAND flash memory BCH codes BCH decoder Hardware complexity Low latency |
| title | Trends and challenges in design of embedded BCH error correction codes in multi-levels NAND flash memory devices |
| title_full | Trends and challenges in design of embedded BCH error correction codes in multi-levels NAND flash memory devices |
| title_fullStr | Trends and challenges in design of embedded BCH error correction codes in multi-levels NAND flash memory devices |
| title_full_unstemmed | Trends and challenges in design of embedded BCH error correction codes in multi-levels NAND flash memory devices |
| title_short | Trends and challenges in design of embedded BCH error correction codes in multi-levels NAND flash memory devices |
| title_sort | trends and challenges in design of embedded bch error correction codes in multi levels nand flash memory devices |
| topic | NAND flash memory BCH codes BCH decoder Hardware complexity Low latency |
| url | http://www.sciencedirect.com/science/article/pii/S277306462400001X |
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