Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETs
650 V SiC planar MOSFETs with various JFET widths, JFET doping concentrations, and gate oxide thicknesses were fabricated by a commercial SiC foundry on two six-inch SiC epitaxial wafers. An orthogonal <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="...
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MDPI AG
2022-08-01
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| Online Access: | https://www.mdpi.com/1996-1944/15/17/5995 |
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| author | Shengnan Zhu Tianshi Liu Junchong Fan Hema Lata Rao Maddi Marvin H. White Anant K. Agarwal |
| author_facet | Shengnan Zhu Tianshi Liu Junchong Fan Hema Lata Rao Maddi Marvin H. White Anant K. Agarwal |
| author_sort | Shengnan Zhu |
| collection | DOAJ |
| description | 650 V SiC planar MOSFETs with various JFET widths, JFET doping concentrations, and gate oxide thicknesses were fabricated by a commercial SiC foundry on two six-inch SiC epitaxial wafers. An orthogonal <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msup><mi mathvariant="normal">P</mi><mo>+</mo></msup></semantics></math></inline-formula> layout was used for the 650 V SiC MOSFETs to reduce the ON-resistance. The devices were packaged into open-cavity TO-247 packages for evaluation. Trade-off analysis of the static and dynamic performance of the 650 V SiC power MOSFETs was conducted. The measurement results show that a short JFET region with an enhanced JFET doping concentration reduces specific ON-resistance (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi mathvariant="normal">R</mi><mrow><mi>on</mi><mo>,</mo><mi>sp</mi></mrow></msub></semantics></math></inline-formula>) and lowers the gate-drain capacitance (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi mathvariant="normal">C</mi><mi>gd</mi></msub></semantics></math></inline-formula>). It was experimentally shown that a thinner gate oxide further reduces <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi mathvariant="normal">R</mi><mrow><mi>on</mi><mo>,</mo><mi>sp</mi></mrow></msub></semantics></math></inline-formula>, although with a penalty in terms of increased <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi mathvariant="normal">C</mi><mi>gd</mi></msub></semantics></math></inline-formula>. A design with 0.5 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>m half JFET width, enhanced JFET doping concentration of <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>5.5</mn><mo>×</mo><msup><mn>10</mn><mn>16</mn></msup></mrow></semantics></math></inline-formula> cm<sup>−3</sup>, and thin gate oxide produces an excellent high-frequency figure of merit (HF-FOM) among recently published studies on 650 V SiC devices. |
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| spelling | doaj.art-93ea600f1c8e4687b84666205a2808f62023-11-23T13:33:48ZengMDPI AGMaterials1996-19442022-08-011517599510.3390/ma15175995Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETsShengnan Zhu0Tianshi Liu1Junchong Fan2Hema Lata Rao Maddi3Marvin H. White4Anant K. Agarwal5Department of Electrical and Computer Engineering, The Ohio State University, Columbus, OH 43210, USADepartment of Electrical and Computer Engineering, The Ohio State University, Columbus, OH 43210, USADepartment of Electrical and Computer Engineering, The Ohio State University, Columbus, OH 43210, USADepartment of Electrical and Computer Engineering, The Ohio State University, Columbus, OH 43210, USADepartment of Electrical and Computer Engineering, The Ohio State University, Columbus, OH 43210, USADepartment of Electrical and Computer Engineering, The Ohio State University, Columbus, OH 43210, USA650 V SiC planar MOSFETs with various JFET widths, JFET doping concentrations, and gate oxide thicknesses were fabricated by a commercial SiC foundry on two six-inch SiC epitaxial wafers. An orthogonal <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msup><mi mathvariant="normal">P</mi><mo>+</mo></msup></semantics></math></inline-formula> layout was used for the 650 V SiC MOSFETs to reduce the ON-resistance. The devices were packaged into open-cavity TO-247 packages for evaluation. Trade-off analysis of the static and dynamic performance of the 650 V SiC power MOSFETs was conducted. The measurement results show that a short JFET region with an enhanced JFET doping concentration reduces specific ON-resistance (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi mathvariant="normal">R</mi><mrow><mi>on</mi><mo>,</mo><mi>sp</mi></mrow></msub></semantics></math></inline-formula>) and lowers the gate-drain capacitance (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi mathvariant="normal">C</mi><mi>gd</mi></msub></semantics></math></inline-formula>). It was experimentally shown that a thinner gate oxide further reduces <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi mathvariant="normal">R</mi><mrow><mi>on</mi><mo>,</mo><mi>sp</mi></mrow></msub></semantics></math></inline-formula>, although with a penalty in terms of increased <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi mathvariant="normal">C</mi><mi>gd</mi></msub></semantics></math></inline-formula>. A design with 0.5 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>m half JFET width, enhanced JFET doping concentration of <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>5.5</mn><mo>×</mo><msup><mn>10</mn><mn>16</mn></msup></mrow></semantics></math></inline-formula> cm<sup>−3</sup>, and thin gate oxide produces an excellent high-frequency figure of merit (HF-FOM) among recently published studies on 650 V SiC devices.https://www.mdpi.com/1996-1944/15/17/5995SiC power MOSFETJFET widthJFET doping concentrationgate oxide thicknessorthogonal P<sup>+</sup> layoutgate-drain capacitance |
| spellingShingle | Shengnan Zhu Tianshi Liu Junchong Fan Hema Lata Rao Maddi Marvin H. White Anant K. Agarwal Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETs Materials SiC power MOSFET JFET width JFET doping concentration gate oxide thickness orthogonal P<sup>+</sup> layout gate-drain capacitance |
| title | Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETs |
| title_full | Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETs |
| title_fullStr | Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETs |
| title_full_unstemmed | Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETs |
| title_short | Effects of JFET Region Design and Gate Oxide Thickness on the Static and Dynamic Performance of 650 V SiC Planar Power MOSFETs |
| title_sort | effects of jfet region design and gate oxide thickness on the static and dynamic performance of 650 v sic planar power mosfets |
| topic | SiC power MOSFET JFET width JFET doping concentration gate oxide thickness orthogonal P<sup>+</sup> layout gate-drain capacitance |
| url | https://www.mdpi.com/1996-1944/15/17/5995 |
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