A Single-Amplifier Dual-Residue Pipelined-SAR ADC
This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the proposed ADC sequentially generates two resid...
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-02-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/10/4/421 |
| _version_ | 1797412448773341184 |
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| author | Min-Jae Seo |
| author_facet | Min-Jae Seo |
| author_sort | Min-Jae Seo |
| collection | DOAJ |
| description | This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the proposed ADC sequentially generates two residue levels from the single RA, which eliminates the need for inter-stage gain-matching calibration. To convert the sequentially generated the two residues, a capacitive interpolating SAR ADC (I-SAR ADC) is also proposed. The I-SAR ADC is very compact because it consists of the one comparator, a CDAC, and control logic like a conventional SAR ADC. In addition, the I-SAR ADC needs no static power dissipation for the residue interpolation. A prototype ADC fabricated in a 40 nm CMOS technology occupies an active area of 0.026 mm<sup>2</sup>. At a 200 MS/s sampling-rate with the Nyquist input, the ADC achieves an SNDR (Signal-to-Noise distortion ratio) of 62.1 dB and 67.1 dB SFDR (Spurious-Free Dynamic Range), respectively. The total power consumed is 3.9 mW under a 0.9 V supply. Without any inter-stage mismatch calibration, the ADC achieve Walden Figure-of-Merit (FoM) of 19.0 fJ/conversion-step. |
| first_indexed | 2024-03-09T05:02:13Z |
| format | Article |
| id | doaj.art-94057879226f48698b2b23eca41b15a3 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-09T05:02:13Z |
| publishDate | 2021-02-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-94057879226f48698b2b23eca41b15a32023-12-03T12:58:29ZengMDPI AGElectronics2079-92922021-02-0110442110.3390/electronics10040421A Single-Amplifier Dual-Residue Pipelined-SAR ADCMin-Jae Seo0School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon 34141, KoreaThis work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the proposed ADC sequentially generates two residue levels from the single RA, which eliminates the need for inter-stage gain-matching calibration. To convert the sequentially generated the two residues, a capacitive interpolating SAR ADC (I-SAR ADC) is also proposed. The I-SAR ADC is very compact because it consists of the one comparator, a CDAC, and control logic like a conventional SAR ADC. In addition, the I-SAR ADC needs no static power dissipation for the residue interpolation. A prototype ADC fabricated in a 40 nm CMOS technology occupies an active area of 0.026 mm<sup>2</sup>. At a 200 MS/s sampling-rate with the Nyquist input, the ADC achieves an SNDR (Signal-to-Noise distortion ratio) of 62.1 dB and 67.1 dB SFDR (Spurious-Free Dynamic Range), respectively. The total power consumed is 3.9 mW under a 0.9 V supply. Without any inter-stage mismatch calibration, the ADC achieve Walden Figure-of-Merit (FoM) of 19.0 fJ/conversion-step.https://www.mdpi.com/2079-9292/10/4/421high speed and high resolutionlow powersuccessive-approximation-register (SAR)analog-to-digital converter (ADC)pipelined-SAR architectureopen-loop residue amplifier |
| spellingShingle | Min-Jae Seo A Single-Amplifier Dual-Residue Pipelined-SAR ADC Electronics high speed and high resolution low power successive-approximation-register (SAR) analog-to-digital converter (ADC) pipelined-SAR architecture open-loop residue amplifier |
| title | A Single-Amplifier Dual-Residue Pipelined-SAR ADC |
| title_full | A Single-Amplifier Dual-Residue Pipelined-SAR ADC |
| title_fullStr | A Single-Amplifier Dual-Residue Pipelined-SAR ADC |
| title_full_unstemmed | A Single-Amplifier Dual-Residue Pipelined-SAR ADC |
| title_short | A Single-Amplifier Dual-Residue Pipelined-SAR ADC |
| title_sort | single amplifier dual residue pipelined sar adc |
| topic | high speed and high resolution low power successive-approximation-register (SAR) analog-to-digital converter (ADC) pipelined-SAR architecture open-loop residue amplifier |
| url | https://www.mdpi.com/2079-9292/10/4/421 |
| work_keys_str_mv | AT minjaeseo asingleamplifierdualresiduepipelinedsaradc AT minjaeseo singleamplifierdualresiduepipelinedsaradc |