A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application

A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application

A design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching...

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Bibliographic Details
Main Authors: Deeksha Verma, Khuram Shehzad, Danial Khan, Sung Jin Kim, Young Gun Pu, Sang-Sun Yoo, Keum Cheol Hwang, Youngoo Yang, Kang-Yoon Lee
Format: Article
Language:English
Published: MDPI AG 2020-07-01
Series:Electronics
Subjects:
asynchronous comparator clock generation
asynchronous successive approximation register (SAR) ADC
capacitive DAC (CDAC)
low power consumption
Online Access:https://www.mdpi.com/2079-9292/9/7/1100

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https://www.mdpi.com/2079-9292/9/7/1100

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