A New Multi-Bit Flip-Flop Merging Mechanism for Power Consumption Reduction in the Physical Implementation Stage of ICs Conception

A New Multi-Bit Flip-Flop Merging Mechanism for Power Consumption Reduction in the Physical Implementation Stage of ICs Conception

Recently, the multi-bit flip-flop (MBFF) technique was introduced as a method for reducing the power consumption and chip area of integrated circuits (ICs) during the physical implementation stage of their development process. From the perspective of the consumer, the main requirements for such an o...

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Bibliographic Details
Main Authors: Lekbir Cherif, Mohamed Chentouf, Jalal Benallal, Mohammed Darmi, Rachid Elgouri, Nabil Hmina
Format: Article
Language:English
Published: MDPI AG 2019-01-01
Series:Journal of Low Power Electronics and Applications
Subjects:
multi-bit flip-flop (MBFF)
low-power design
physical implementation
power optimization
integrated circuit performance
chip area
Online Access:https://www.mdpi.com/2079-9268/9/1/3

Internet

https://www.mdpi.com/2079-9268/9/1/3

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