A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With >55-dBFS SNR and >67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI
In this article, a 3-GS/s time-interleaved (TI) RF track-and-hold (TaH) amplifier designed in a 22-nm SOI technology is presented. The TaH amplifier is designed to drive an ADC, which can be either two pipeline-ADCs or two rows of SAR-ADCs. Both TI TaH are driven by a single RF-matched wide-band bul...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2022-01-01
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| Series: | IEEE Open Journal of the Solid-State Circuits Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9928330/ |
| _version_ | 1797197406746443776 |
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| author | Enne Wittenhagen Patrick James Artz Philipp Scholz Friedel Gerfers |
| author_facet | Enne Wittenhagen Patrick James Artz Philipp Scholz Friedel Gerfers |
| author_sort | Enne Wittenhagen |
| collection | DOAJ |
| description | In this article, a 3-GS/s time-interleaved (TI) RF track-and-hold (TaH) amplifier designed in a 22-nm SOI technology is presented. The TaH amplifier is designed to drive an ADC, which can be either two pipeline-ADCs or two rows of SAR-ADCs. Both TI TaH are driven by a single RF-matched wide-band bulk-controlled front-end (FE) buffer. The measured TaH amplifier has an SFDR beyond 70 dBc up to 2.5 GHz and remains above 67 dBc till 3 GHz enabling subsampling. An overall system bandwidth of 4.5 GHz is achieved with an SNR above 55 dBFS. The ultralow-jitter clock regeneration has only 45 fs rms jitter not limiting the SNR up to 3 GHz. Two-tone and multitone measurements reveal a third intermodulation and interband nonlinearity with >72 and >82 dBFS, respectively. Off-chip calibration of offset/gain mismatch and time-skew between both TaH-lanes reduce interleaving spurs >75 dBFS utilizing a 37-tap fractional delay FIR filter. The efficient body-bias control of the technology is used to dynamically body-bias the TaH sample-switch increasing bandwidth by 10% improving settling performance while at the same time the leakage decreases. Static body-biasing is also applied to the common-mode feedback by using the bulk as a control node. The TaH amplifier including the clock generation consumes only 178 mW from a triple 2 V/0.9 V/−0.8 V supply. |
| first_indexed | 2024-04-24T06:43:28Z |
| format | Article |
| id | doaj.art-95ff94c6aac74b3f84f06faff8d46d37 |
| institution | Directory Open Access Journal |
| issn | 2644-1349 |
| language | English |
| last_indexed | 2024-04-24T06:43:28Z |
| publishDate | 2022-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of the Solid-State Circuits Society |
| spelling | doaj.art-95ff94c6aac74b3f84f06faff8d46d372024-04-22T20:40:02ZengIEEEIEEE Open Journal of the Solid-State Circuits Society2644-13492022-01-01213514310.1109/OJSSCS.2022.32170199928330A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With >55-dBFS SNR and >67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOIEnne Wittenhagen0https://orcid.org/0000-0001-8282-2128Patrick James Artz1Philipp Scholz2https://orcid.org/0000-0002-7209-3117Friedel Gerfers3https://orcid.org/0000-0002-0520-1923Chair of Mixed Signal Circuit Design, Technische Universität Berlin, Berlin, GermanyChair of Mixed Signal Circuit Design, Technische Universität Berlin, Berlin, GermanyChair of Mixed Signal Circuit Design, Technische Universität Berlin, Berlin, GermanyChair of Mixed Signal Circuit Design, Technische Universität Berlin, Berlin, GermanyIn this article, a 3-GS/s time-interleaved (TI) RF track-and-hold (TaH) amplifier designed in a 22-nm SOI technology is presented. The TaH amplifier is designed to drive an ADC, which can be either two pipeline-ADCs or two rows of SAR-ADCs. Both TI TaH are driven by a single RF-matched wide-band bulk-controlled front-end (FE) buffer. The measured TaH amplifier has an SFDR beyond 70 dBc up to 2.5 GHz and remains above 67 dBc till 3 GHz enabling subsampling. An overall system bandwidth of 4.5 GHz is achieved with an SNR above 55 dBFS. The ultralow-jitter clock regeneration has only 45 fs rms jitter not limiting the SNR up to 3 GHz. Two-tone and multitone measurements reveal a third intermodulation and interband nonlinearity with >72 and >82 dBFS, respectively. Off-chip calibration of offset/gain mismatch and time-skew between both TaH-lanes reduce interleaving spurs >75 dBFS utilizing a 37-tap fractional delay FIR filter. The efficient body-bias control of the technology is used to dynamically body-bias the TaH sample-switch increasing bandwidth by 10% improving settling performance while at the same time the leakage decreases. Static body-biasing is also applied to the common-mode feedback by using the bulk as a control node. The TaH amplifier including the clock generation consumes only 178 mW from a triple 2 V/0.9 V/−0.8 V supply.https://ieeexplore.ieee.org/document/9928330/Body-biasingcommon-mode feedback (CMFB)FD-SOIfront-end (FE)RFtime interleaving (TI) |
| spellingShingle | Enne Wittenhagen Patrick James Artz Philipp Scholz Friedel Gerfers A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With >55-dBFS SNR and >67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI IEEE Open Journal of the Solid-State Circuits Society Body-biasing common-mode feedback (CMFB) FD-SOI front-end (FE) RF time interleaving (TI) |
| title | A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With >55-dBFS SNR and >67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI |
| title_full | A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With >55-dBFS SNR and >67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI |
| title_fullStr | A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With >55-dBFS SNR and >67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI |
| title_full_unstemmed | A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With >55-dBFS SNR and >67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI |
| title_short | A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With >55-dBFS SNR and >67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI |
| title_sort | 3 gs s rf track and hold amplifier utilizing body biasing with x003e 55 dbfs snr and x003e 67 dbc sfdr up to 3 ghz in 22 nm cmos soi |
| topic | Body-biasing common-mode feedback (CMFB) FD-SOI front-end (FE) RF time interleaving (TI) |
| url | https://ieeexplore.ieee.org/document/9928330/ |
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