Implementation and modeling of parametrizable high-speed Reed Solomon decoders on FPGAs
One of the most important error correction codes in digital signal processing is the Reed Solomon code. A lot of VLSI implementations have been described in literature. This paper introduces a highly parametrizable RS-decoder for FPGAs. By implementing resource-sharing and by using a fully pipelined...
| Main Authors: | , , |
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| Format: | Article |
| Language: | deu |
| Published: |
Copernicus Publications
2005-01-01
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| Series: | Advances in Radio Science |
| Online Access: | http://www.adv-radio-sci.net/3/271/2005/ars-3-271-2005.pdf |