Theoretical Modeling and Simulation of Phase-Locked Loop (PLL) for Clock Data Recovery (CDR)
Modern communication and computer systems require rapid (Gbps), efficient and large bandwidth data transfers. Agressive scaling of digital integrated systems allow buses and communication controller circuits to be integrated with the microprocessor on the same chip. The Peripheral Component Inter...
| Główni autorzy: | , |
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| Format: | Artykuł |
| Język: | English |
| Wydane: |
IIUM Press, International Islamic University Malaysia
2012-01-01
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| Seria: | International Islamic University Malaysia Engineering Journal |
| Dostęp online: | http://journals.iium.edu.my/ejournal/index.php/iiumej/article/view/250 |