Design of a high-performance and dynamic reconfigurable SPI IP core with master and slave mode
To meet the flexible configuration requirements of serial peripheral interface(SPI) in the System-on-a-Chip(SoC), the SPI IP core which can be configured as a master or slave with four date transfer modes and seven clock transmission rates is designed. The SPI IP core through the state machine contr...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | zho |
| Published: |
National Computer System Engineering Research Institute of China
2018-03-01
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| Series: | Dianzi Jishu Yingyong |
| Subjects: | |
| Online Access: | http://www.chinaaet.com/article/3000078548 |