Design of a high-performance and dynamic reconfigurable SPI IP core with master and slave mode
To meet the flexible configuration requirements of serial peripheral interface(SPI) in the System-on-a-Chip(SoC), the SPI IP core which can be configured as a master or slave with four date transfer modes and seven clock transmission rates is designed. The SPI IP core through the state machine contr...
| Main Authors: | , , , , |
|---|---|
| Format: | Article |
| Language: | zho |
| Published: |
National Computer System Engineering Research Institute of China
2018-03-01
|
| Series: | Dianzi Jishu Yingyong |
| Subjects: | |
| Online Access: | http://www.chinaaet.com/article/3000078548 |
| _version_ | 1819032291377152000 |
|---|---|
| author | Wei Pengbo Zhang Cunde Huang Xiang Yu Zhiguo GU Xiaofeng |
| author_facet | Wei Pengbo Zhang Cunde Huang Xiang Yu Zhiguo GU Xiaofeng |
| author_sort | Wei Pengbo |
| collection | DOAJ |
| description | To meet the flexible configuration requirements of serial peripheral interface(SPI) in the System-on-a-Chip(SoC), the SPI IP core which can be configured as a master or slave with four date transfer modes and seven clock transmission rates is designed. The SPI IP core through the state machine controls the port direction of data transmission module, which solves the problem of the opposite direction of data transmission in master and slave mode. The SPI IP core also multiplexes the shift register to reduce logic resource consumption. The clock frequency division module is designed to realize the data exchange with different transmission rates. In order to facilitate the operation of the SPI IP core, the ports including cpol and cpha that can configure the data transfer modes are designed. The results show that the SPI IP core is in good agreement with the SPI bus protocol. In addition, the circuit scale contains 1 062 logic gates under the 0.13 μm technology and the power consumption is 0.395 7 mW at a system operating frequency of 80 MHz. |
| first_indexed | 2024-12-21T06:59:36Z |
| format | Article |
| id | doaj.art-984cc7b17a074816b9d74684d287a154 |
| institution | Directory Open Access Journal |
| issn | 0258-7998 |
| language | zho |
| last_indexed | 2024-12-21T06:59:36Z |
| publishDate | 2018-03-01 |
| publisher | National Computer System Engineering Research Institute of China |
| record_format | Article |
| series | Dianzi Jishu Yingyong |
| spelling | doaj.art-984cc7b17a074816b9d74684d287a1542022-12-21T19:12:15ZzhoNational Computer System Engineering Research Institute of ChinaDianzi Jishu Yingyong0258-79982018-03-01443151810.16157/j.issn.0258-7998.1728383000078548Design of a high-performance and dynamic reconfigurable SPI IP core with master and slave modeWei Pengbo0Zhang Cunde1Huang Xiang2Yu Zhiguo3GU Xiaofeng4Engineering Research Center of IoT Technology Applications(Ministry of Education)，Wuxi 214122，ChinaEngineering Research Center of IoT Technology Applications(Ministry of Education)，Wuxi 214122，ChinaEngineering Research Center of IoT Technology Applications(Ministry of Education)，Wuxi 214122，ChinaEngineering Research Center of IoT Technology Applications(Ministry of Education)，Wuxi 214122，ChinaEngineering Research Center of IoT Technology Applications(Ministry of Education)，Wuxi 214122，ChinaTo meet the flexible configuration requirements of serial peripheral interface(SPI) in the System-on-a-Chip(SoC), the SPI IP core which can be configured as a master or slave with four date transfer modes and seven clock transmission rates is designed. The SPI IP core through the state machine controls the port direction of data transmission module, which solves the problem of the opposite direction of data transmission in master and slave mode. The SPI IP core also multiplexes the shift register to reduce logic resource consumption. The clock frequency division module is designed to realize the data exchange with different transmission rates. In order to facilitate the operation of the SPI IP core, the ports including cpol and cpha that can configure the data transfer modes are designed. The results show that the SPI IP core is in good agreement with the SPI bus protocol. In addition, the circuit scale contains 1 062 logic gates under the 0.13 μm technology and the power consumption is 0.395 7 mW at a system operating frequency of 80 MHz.http://www.chinaaet.com/article/3000078548high-performancemaster and slave modedynamic reconfigurableserial peripheral interface(SPI)IP core |
| spellingShingle | Wei Pengbo Zhang Cunde Huang Xiang Yu Zhiguo GU Xiaofeng Design of a high-performance and dynamic reconfigurable SPI IP core with master and slave mode Dianzi Jishu Yingyong high-performance master and slave mode dynamic reconfigurable serial peripheral interface(SPI) IP core |
| title | Design of a high-performance and dynamic reconfigurable SPI IP core with master and slave mode |
| title_full | Design of a high-performance and dynamic reconfigurable SPI IP core with master and slave mode |
| title_fullStr | Design of a high-performance and dynamic reconfigurable SPI IP core with master and slave mode |
| title_full_unstemmed | Design of a high-performance and dynamic reconfigurable SPI IP core with master and slave mode |
| title_short | Design of a high-performance and dynamic reconfigurable SPI IP core with master and slave mode |
| title_sort | design of a high performance and dynamic reconfigurable spi ip core with master and slave mode |
| topic | high-performance master and slave mode dynamic reconfigurable serial peripheral interface(SPI) IP core |
| url | http://www.chinaaet.com/article/3000078548 |
| work_keys_str_mv | AT weipengbo designofahighperformanceanddynamicreconfigurablespiipcorewithmasterandslavemode AT zhangcunde designofahighperformanceanddynamicreconfigurablespiipcorewithmasterandslavemode AT huangxiang designofahighperformanceanddynamicreconfigurablespiipcorewithmasterandslavemode AT yuzhiguo designofahighperformanceanddynamicreconfigurablespiipcorewithmasterandslavemode AT guxiaofeng designofahighperformanceanddynamicreconfigurablespiipcorewithmasterandslavemode |