DSCU: Accelerating CNN Inference in FPGAs with Dual Sizes of Compute Unit
FPGA-based accelerators have shown great potential in improving the performance of CNN inference. However, the existing FPGA-based approaches suffer from a low compute unit (CU) efficiency due to their large number of redundant computations, thus leading to high levels of performance degradation. In...
| Main Authors: | , , , |
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| 格式: | 文件 |
| 语言: | English |
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MDPI AG
2022-02-01
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| 丛编: | Journal of Low Power Electronics and Applications |
| 主题: | |
| 在线阅读: | https://www.mdpi.com/2079-9268/12/1/11 |