Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes

Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes

Many-tier vertical gate-all-around nanowire FET (VFET) synthesis strongly demands a holistic approach of modeling/formulating/optimizing transistor placement and in-cell routing to obtain the maximum-achievable power, performance, area, and cost (PPAC) benefits. In this article, we propose a novel s...

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Bibliographic Details
Main Authors: Daeyeal Lee, Chia-Tung Ho, Ilgweon Kang, Sicun Gao, Bill Lin, Chung-Kuan Cheng
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Subjects:
Automatic standard cell (SDC) generation
constraint satisfaction problem (CSP)
gateall-around (GAA)FET
pin accessibility
satisfiability modulo theories (SMT)
vertical GAA nanowire FET (VFET)
Online Access:https://ieeexplore.ieee.org/document/9454552/

Internet

https://ieeexplore.ieee.org/document/9454552/

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