Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes
Many-tier vertical gate-all-around nanowire FET (VFET) synthesis strongly demands a holistic approach of modeling/formulating/optimizing transistor placement and in-cell routing to obtain the maximum-achievable power, performance, area, and cost (PPAC) benefits. In this article, we propose a novel s...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2021-01-01
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| Series: | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9454552/ |