Efficient Memory Organization for DNN Hardware Accelerator Implementation on PSoC

Efficient Memory Organization for DNN Hardware Accelerator Implementation on PSoC

The use of deep learning solutions in different disciplines is increasing and their algorithms are computationally expensive in most cases. For this reason, numerous hardware accelerators have appeared to compute their operations efficiently in parallel, achieving higher performance and lower latenc...

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Bibliographic Details
Main Authors: Antonio Rios-Navarro, Daniel Gutierrez-Galan, Juan Pedro Dominguez-Morales, Enrique Piñero-Fuentes, Lourdes Duran-Lopez, Ricardo Tapiador-Morales, Manuel Jesús Dominguez-Morales
Format: Article
Language:English
Published: MDPI AG 2021-01-01
Series:Electronics
Subjects:
deep learning
embedded systems
PSoC
memory organization
FPGA
hardware accelerator
Online Access:https://www.mdpi.com/2079-9292/10/1/94

Internet

https://www.mdpi.com/2079-9292/10/1/94

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