A Technique to Improve the Performance of an NPN HBT on Thin-Film SOI
The performance of an npn SiGe HBT on thin-film silicon on insulator (SOI) is investigated using 2-D numerical simulation. A technique of using N+ buried layer has been presented to improve the performance of an SiGe HBT on thin-film SOI. The tradeoff in the performance of HBT has been observed and...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2013-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/6482578/ |