A Technique to Improve the Performance of an NPN HBT on Thin-Film SOI
The performance of an npn SiGe HBT on thin-film silicon on insulator (SOI) is investigated using 2-D numerical simulation. A technique of using N+ buried layer has been presented to improve the performance of an SiGe HBT on thin-film SOI. The tradeoff in the performance of HBT has been observed and...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2013-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/6482578/ |
| Summary: | The performance of an npn SiGe HBT on thin-film silicon on insulator (SOI) is investigated using 2-D numerical simulation. A technique of using N+ buried layer has been presented to improve the performance of an SiGe HBT on thin-film SOI. The tradeoff in the performance of HBT has been observed and the results are compared to the standard SOI HBT. The HBT offers better βV<sub>A</sub> product at high collector currents. A 341 GHzV of f<sub>t</sub>BV<sub>CEO</sub> product can be obtained by using this technique. The scalability of film thickness is applied and the enhancement in the speed is observed. The self-heating performance of the proposed HBT is studied and the BOX thickness has been scaled to improve the thermal performance. The maximum lattice temperature is obtained. The proposed HBT is suitable for RF applications and can be used in addition to the existing 130 nm SOI CMOS technology for better performance. |
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| ISSN: | 2168-6734 |