AESware: Developing AES-enabled low-power multicore processors leveraging open RISC-V cores with a shared lightweight AES accelerator

AESware: Developing AES-enabled low-power multicore processors leveraging open RISC-V cores with a shared lightweight AES accelerator

As open-source RISC-V cores continue to be released, the development of low-power multicore processors utilizing these cores is invigorating the edge/IoT device market. Nevertheless, comprehensive research on developing low-power multicore processors with integrated security features using existing...

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Bibliographic Details
Main Authors: Eunjin Choi, Jina Park, Kyuseung Han, Woojoo Lee
Format: Article
Language:English
Published: Elsevier 2024-12-01
Series:Engineering Science and Technology, an International Journal
Subjects:
Edge device
AES
RISC-V
Embedded processor
Multi-core processor architecture
FPGA prototyping
Online Access:http://www.sciencedirect.com/science/article/pii/S2215098624002805

Internet

http://www.sciencedirect.com/science/article/pii/S2215098624002805

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