Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors
In this paper, we present an artificial neural network (ANN)-based compact model to evaluate the characteristics of a nanosheet field-effect transistor (NSFET), which has been highlighted as a next-generation nano-device. To extract data reflecting the accurate physical characteristics of NSFETs, th...
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-09-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/11/17/2761 |
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| author | SangMin Woo HyunJoon Jeong JinYoung Choi HyungMin Cho Jeong-Taek Kong SoYoung Kim |
| author_facet | SangMin Woo HyunJoon Jeong JinYoung Choi HyungMin Cho Jeong-Taek Kong SoYoung Kim |
| author_sort | SangMin Woo |
| collection | DOAJ |
| description | In this paper, we present an artificial neural network (ANN)-based compact model to evaluate the characteristics of a nanosheet field-effect transistor (NSFET), which has been highlighted as a next-generation nano-device. To extract data reflecting the accurate physical characteristics of NSFETs, the Sentaurus TCAD (technology computer-aided design) simulator was used. The proposed ANN model accurately and efficiently predicts currents and capacitances of devices using the five proposed key geometric parameters and two voltage biases. A variety of experiments were carried out in order to create a powerful ANN-based compact model using a large amount of data up to the sub-3-nm node. In addition, the activation function, physics-augmented loss function, ANN structure, and preprocessing methods were used for effective and efficient ANN learning. The proposed model was implemented in Verilog-A. Both a global device model and a single-device model were developed, and their accuracy and speed were compared to those of the existing compact model. The proposed ANN-based compact model simulates device characteristics and circuit performances with high accuracy and speed. This is the first time that a machine learning (ML)-based compact model has been demonstrated to be several times faster than the existing compact model. |
| first_indexed | 2024-03-10T01:54:12Z |
| format | Article |
| id | doaj.art-9e341fd43cc749d28628594b0c37cf77 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T01:54:12Z |
| publishDate | 2022-09-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-9e341fd43cc749d28628594b0c37cf772023-11-23T12:59:34ZengMDPI AGElectronics2079-92922022-09-011117276110.3390/electronics11172761Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging TransistorsSangMin Woo0HyunJoon Jeong1JinYoung Choi2HyungMin Cho3Jeong-Taek Kong4SoYoung Kim5College of Information and Communication Engineering, SungKyunKwan University, Suwon 16419, KoreaCollege of Information and Communication Engineering, SungKyunKwan University, Suwon 16419, KoreaCollege of Information and Communication Engineering, SungKyunKwan University, Suwon 16419, KoreaCollege of Information and Communication Engineering, SungKyunKwan University, Suwon 16419, KoreaCollege of Information and Communication Engineering, SungKyunKwan University, Suwon 16419, KoreaCollege of Information and Communication Engineering, SungKyunKwan University, Suwon 16419, KoreaIn this paper, we present an artificial neural network (ANN)-based compact model to evaluate the characteristics of a nanosheet field-effect transistor (NSFET), which has been highlighted as a next-generation nano-device. To extract data reflecting the accurate physical characteristics of NSFETs, the Sentaurus TCAD (technology computer-aided design) simulator was used. The proposed ANN model accurately and efficiently predicts currents and capacitances of devices using the five proposed key geometric parameters and two voltage biases. A variety of experiments were carried out in order to create a powerful ANN-based compact model using a large amount of data up to the sub-3-nm node. In addition, the activation function, physics-augmented loss function, ANN structure, and preprocessing methods were used for effective and efficient ANN learning. The proposed model was implemented in Verilog-A. Both a global device model and a single-device model were developed, and their accuracy and speed were compared to those of the existing compact model. The proposed ANN-based compact model simulates device characteristics and circuit performances with high accuracy and speed. This is the first time that a machine learning (ML)-based compact model has been demonstrated to be several times faster than the existing compact model.https://www.mdpi.com/2079-9292/11/17/2761artificial neural networkcompact modelnanosheet FETsTCAD/SPICE simulation |
| spellingShingle | SangMin Woo HyunJoon Jeong JinYoung Choi HyungMin Cho Jeong-Taek Kong SoYoung Kim Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors Electronics artificial neural network compact model nanosheet FETs TCAD/SPICE simulation |
| title | Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors |
| title_full | Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors |
| title_fullStr | Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors |
| title_full_unstemmed | Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors |
| title_short | Machine-Learning-Based Compact Modeling for Sub-3-nm-Node Emerging Transistors |
| title_sort | machine learning based compact modeling for sub 3 nm node emerging transistors |
| topic | artificial neural network compact model nanosheet FETs TCAD/SPICE simulation |
| url | https://www.mdpi.com/2079-9292/11/17/2761 |
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