Boosting RRAM-Based Mixed-Signal Accelerators in FD-SOI Technology for ML Applications
This article presents the flipped (F)-2T2R resistive random access memory (RRAM) compute cell enhancing the performance of RRAM-based mixed-signal accelerators for deep neural networks (DNNs) in machine-learning (ML) applications. The F-2T2R cell is designed to exploit the features of the FD-SOI tec...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2023-01-01
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| Series: | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10233848/ |
| _version_ | 1797338496766050304 |
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| author | Andrea Boni Francesco Malena Francesco Saccani Michele Amoretti Michele Caselli |
| author_facet | Andrea Boni Francesco Malena Francesco Saccani Michele Amoretti Michele Caselli |
| author_sort | Andrea Boni |
| collection | DOAJ |
| description | This article presents the flipped (F)-2T2R resistive random access memory (RRAM) compute cell enhancing the performance of RRAM-based mixed-signal accelerators for deep neural networks (DNNs) in machine-learning (ML) applications. The F-2T2R cell is designed to exploit the features of the FD-SOI technology and it achieves a large increase in cell output impedance, compared to the standard 1-transistor 1-resistor (1T1R) cell. The article also describes the modeling of an F-2T2R-based accelerator and its transistor-level implementation in a 22-nm FD-SOI technology. The modeling results and the accelerator performance are validated by simulation. The proposed design can achieve an energy efficiency of up to 1260 1 bit-TOPS/W, with a memory array of 256 rows and columns. From the results of our analytical framework, a ResNet18, mapped on the accelerator, can obtain an accuracy reduction below 2%, with respect to the floating-point baseline, on the CIFAR-10 dataset. |
| first_indexed | 2024-03-08T09:32:06Z |
| format | Article |
| id | doaj.art-9e67aea22ed44814bf0a3db8e7495b83 |
| institution | Directory Open Access Journal |
| issn | 2329-9231 |
| language | English |
| last_indexed | 2024-03-08T09:32:06Z |
| publishDate | 2023-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| spelling | doaj.art-9e67aea22ed44814bf0a3db8e7495b832024-01-31T00:01:54ZengIEEEIEEE Journal on Exploratory Solid-State Computational Devices and Circuits2329-92312023-01-019215916710.1109/JXCDC.2023.330971310233848Boosting RRAM-Based Mixed-Signal Accelerators in FD-SOI Technology for ML ApplicationsAndrea Boni0https://orcid.org/0000-0001-7649-2871Francesco Malena1Francesco Saccani2https://orcid.org/0000-0002-9585-7394Michele Amoretti3https://orcid.org/0000-0002-6046-1904Michele Caselli4https://orcid.org/0000-0003-3807-8033Department of Engineering and Architecture, University of Parma, Parma, ItalyDepartment of Engineering and Architecture, University of Parma, Parma, ItalyDepartment of Engineering and Architecture, University of Parma, Parma, ItalyDepartment of Engineering and Architecture, University of Parma, Parma, ItalyDepartment of Engineering and Architecture, University of Parma, Parma, ItalyThis article presents the flipped (F)-2T2R resistive random access memory (RRAM) compute cell enhancing the performance of RRAM-based mixed-signal accelerators for deep neural networks (DNNs) in machine-learning (ML) applications. The F-2T2R cell is designed to exploit the features of the FD-SOI technology and it achieves a large increase in cell output impedance, compared to the standard 1-transistor 1-resistor (1T1R) cell. The article also describes the modeling of an F-2T2R-based accelerator and its transistor-level implementation in a 22-nm FD-SOI technology. The modeling results and the accelerator performance are validated by simulation. The proposed design can achieve an energy efficiency of up to 1260 1 bit-TOPS/W, with a memory array of 256 rows and columns. From the results of our analytical framework, a ResNet18, mapped on the accelerator, can obtain an accuracy reduction below 2%, with respect to the floating-point baseline, on the CIFAR-10 dataset.https://ieeexplore.ieee.org/document/10233848/Analog in-memory computingconvolutional neural networksFD-SOImixed-signal acceleratorsresistive random access memory (RRAM) |
| spellingShingle | Andrea Boni Francesco Malena Francesco Saccani Michele Amoretti Michele Caselli Boosting RRAM-Based Mixed-Signal Accelerators in FD-SOI Technology for ML Applications IEEE Journal on Exploratory Solid-State Computational Devices and Circuits Analog in-memory computing convolutional neural networks FD-SOI mixed-signal accelerators resistive random access memory (RRAM) |
| title | Boosting RRAM-Based Mixed-Signal Accelerators in FD-SOI Technology for ML Applications |
| title_full | Boosting RRAM-Based Mixed-Signal Accelerators in FD-SOI Technology for ML Applications |
| title_fullStr | Boosting RRAM-Based Mixed-Signal Accelerators in FD-SOI Technology for ML Applications |
| title_full_unstemmed | Boosting RRAM-Based Mixed-Signal Accelerators in FD-SOI Technology for ML Applications |
| title_short | Boosting RRAM-Based Mixed-Signal Accelerators in FD-SOI Technology for ML Applications |
| title_sort | boosting rram based mixed signal accelerators in fd soi technology for ml applications |
| topic | Analog in-memory computing convolutional neural networks FD-SOI mixed-signal accelerators resistive random access memory (RRAM) |
| url | https://ieeexplore.ieee.org/document/10233848/ |
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