Parameterized Hardware Accelerators for Lattice-Based Cryptography and Their Application to the HW/SW Co-Design of qTESLA

Parameterized Hardware Accelerators for Lattice-Based Cryptography and Their Application to the HW/SW Co-Design of qTESLA

This paper presents a set of efficient and parameterized hardware accelerators that target post-quantum lattice-based cryptographic schemes, including a versatile cSHAKE core, a binary-search CDT-based Gaussian sampler, and a pipelined NTT-based polynomial multiplier, among others. Unlike much of pr...

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Bibliographic Details
Main Authors: Wen Wang, Shanquan Tian, Bernhard Jungk, Nina Bindel, Patrick Longa, Jakub Szefer
Format: Article
Language:English
Published: Ruhr-Universität Bochum 2020-06-01
Series:Transactions on Cryptographic Hardware and Embedded Systems
Subjects:
Lattice-based cryptography
Post-quantum cryptography
qTESLA
Hardware accelerators
Hardware-software co-design
FPGA
Online Access:https://tches.iacr.org/index.php/TCHES/article/view/8591

Internet

https://tches.iacr.org/index.php/TCHES/article/view/8591

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