Parameterized Hardware Accelerators for Lattice-Based Cryptography and Their Application to the HW/SW Co-Design of qTESLA
This paper presents a set of efficient and parameterized hardware accelerators that target post-quantum lattice-based cryptographic schemes, including a versatile cSHAKE core, a binary-search CDT-based Gaussian sampler, and a pipelined NTT-based polynomial multiplier, among others. Unlike much of pr...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
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Ruhr-Universität Bochum
2020-06-01
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| Series: | Transactions on Cryptographic Hardware and Embedded Systems |
| Subjects: | |
| Online Access: | https://tches.iacr.org/index.php/TCHES/article/view/8591 |
| _version_ | 1818084993937702912 |
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| author | Wen Wang Shanquan Tian Bernhard Jungk Nina Bindel Patrick Longa Jakub Szefer |
| author_facet | Wen Wang Shanquan Tian Bernhard Jungk Nina Bindel Patrick Longa Jakub Szefer |
| author_sort | Wen Wang |
| collection | DOAJ |
| description | This paper presents a set of efficient and parameterized hardware accelerators that target post-quantum lattice-based cryptographic schemes, including a versatile cSHAKE core, a binary-search CDT-based Gaussian sampler, and a pipelined NTT-based polynomial multiplier, among others. Unlike much of prior work, the accelerators are fully open-sourced, are designed to be constant-time, and can be parameterized at compile-time to support different parameters without the need for re-writing the hardware implementation. These flexible, publicly-available accelerators are leveraged to demonstrate the first hardware-software co-design using RISC-V of the post-quantum lattice-based signature scheme qTESLA with provably secure parameters. In particular, this work demonstrates that the NIST’s Round 2 level 1 and level 3 qTESLA variants achieve over a 40-100x speedup for key generation, about a 10x speedup for signing, and about a 16x speedup for verification, compared to the baseline RISC-V software-only implementation. For instance, this corresponds to execution in 7.7, 34.4, and 7.8 milliseconds for key generation, signing, and verification, respectively, for qTESLA’s level 1 parameter set on an Artix-7 FPGA, demonstrating the feasibility of the scheme for embedded applications. |
| first_indexed | 2024-12-10T20:02:43Z |
| format | Article |
| id | doaj.art-a115186b82554689bb7b9a933d942918 |
| institution | Directory Open Access Journal |
| issn | 2569-2925 |
| language | English |
| last_indexed | 2024-12-10T20:02:43Z |
| publishDate | 2020-06-01 |
| publisher | Ruhr-Universität Bochum |
| record_format | Article |
| series | Transactions on Cryptographic Hardware and Embedded Systems |
| spelling | doaj.art-a115186b82554689bb7b9a933d9429182022-12-22T01:35:29ZengRuhr-Universität BochumTransactions on Cryptographic Hardware and Embedded Systems2569-29252020-06-012020310.13154/tches.v2020.i3.269-306Parameterized Hardware Accelerators for Lattice-Based Cryptography and Their Application to the HW/SW Co-Design of qTESLAWen Wang0Shanquan Tian1Bernhard Jungk2Nina Bindel3Patrick Longa4Jakub Szefer5Yale University, USAYale University, USAMAN Truck & Bus SE, GermanyUniversity of Waterloo, CanadaMicrosoft Research, USAYale University, USAThis paper presents a set of efficient and parameterized hardware accelerators that target post-quantum lattice-based cryptographic schemes, including a versatile cSHAKE core, a binary-search CDT-based Gaussian sampler, and a pipelined NTT-based polynomial multiplier, among others. Unlike much of prior work, the accelerators are fully open-sourced, are designed to be constant-time, and can be parameterized at compile-time to support different parameters without the need for re-writing the hardware implementation. These flexible, publicly-available accelerators are leveraged to demonstrate the first hardware-software co-design using RISC-V of the post-quantum lattice-based signature scheme qTESLA with provably secure parameters. In particular, this work demonstrates that the NIST’s Round 2 level 1 and level 3 qTESLA variants achieve over a 40-100x speedup for key generation, about a 10x speedup for signing, and about a 16x speedup for verification, compared to the baseline RISC-V software-only implementation. For instance, this corresponds to execution in 7.7, 34.4, and 7.8 milliseconds for key generation, signing, and verification, respectively, for qTESLA’s level 1 parameter set on an Artix-7 FPGA, demonstrating the feasibility of the scheme for embedded applications.https://tches.iacr.org/index.php/TCHES/article/view/8591Lattice-based cryptographyPost-quantum cryptographyqTESLAHardware acceleratorsHardware-software co-designFPGA |
| spellingShingle | Wen Wang Shanquan Tian Bernhard Jungk Nina Bindel Patrick Longa Jakub Szefer Parameterized Hardware Accelerators for Lattice-Based Cryptography and Their Application to the HW/SW Co-Design of qTESLA Transactions on Cryptographic Hardware and Embedded Systems Lattice-based cryptography Post-quantum cryptography qTESLA Hardware accelerators Hardware-software co-design FPGA |
| title | Parameterized Hardware Accelerators for Lattice-Based Cryptography and Their Application to the HW/SW Co-Design of qTESLA |
| title_full | Parameterized Hardware Accelerators for Lattice-Based Cryptography and Their Application to the HW/SW Co-Design of qTESLA |
| title_fullStr | Parameterized Hardware Accelerators for Lattice-Based Cryptography and Their Application to the HW/SW Co-Design of qTESLA |
| title_full_unstemmed | Parameterized Hardware Accelerators for Lattice-Based Cryptography and Their Application to the HW/SW Co-Design of qTESLA |
| title_short | Parameterized Hardware Accelerators for Lattice-Based Cryptography and Their Application to the HW/SW Co-Design of qTESLA |
| title_sort | parameterized hardware accelerators for lattice based cryptography and their application to the hw sw co design of qtesla |
| topic | Lattice-based cryptography Post-quantum cryptography qTESLA Hardware accelerators Hardware-software co-design FPGA |
| url | https://tches.iacr.org/index.php/TCHES/article/view/8591 |
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