A 16-Bit 1-MS/s Pseudo-Differential SAR ADC With Digital Calibration and DNL Enhancement Achieving 92 dB SNDR
This paper presents a 16-bit 1 MS/s pseudo-differential Successive-Approximation-Register Analog-to-Digital Converter (SAR ADC) achieving an ENOB of 15-bit. To accommodate the pseudo-differential input, a differential DAC utilizing both monotonic and traditional switching is designed. For both dynam...
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| Format: | Article |
| Language: | English |
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IEEE
2019-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/8812735/ |
| _version_ | 1811274524643033088 |
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| author | Panpan Zhang Wenjiang Feng Peng Zhao Xiaoping Chen Zongjiang Zhang |
| author_facet | Panpan Zhang Wenjiang Feng Peng Zhao Xiaoping Chen Zongjiang Zhang |
| author_sort | Panpan Zhang |
| collection | DOAJ |
| description | This paper presents a 16-bit 1 MS/s pseudo-differential Successive-Approximation-Register Analog-to-Digital Converter (SAR ADC) achieving an ENOB of 15-bit. To accommodate the pseudo-differential input, a differential DAC utilizing both monotonic and traditional switching is designed. For both dynamic and static performance improvement, three techniques are proposed. First, a foreground digital self-calibration method is described to eliminate the capacitor mismatch errors. Some of the LSBs capacitors are utilized to measure and calculate the bit weights of other capacitors. Second, a DNL enhancement technique is presented. The fractional value capacitors are used to subtract an analog voltage from the DAC before the conversion is finished, which cancels out the consequent effect when the fractional part of the digital output is discarded before final output. Third, a low-offset low-noise comparator is designed. A reset timer with DAC settling replica is proposed to make the pre-amplifier in the comparator to start to amplify the DAC summing node voltage right after the DAC has fully settled. A prototype ADC is fabricated in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> 5-V CMOS process. It measures a 92.3-dB SNDR and a 107.9-dB SFDR. The DNL and INL are within ±0.3 LSB and ±0.72 LSB, respectively. The overall power consumption, drawn from the 5 V power supply, is 40 mW. |
| first_indexed | 2024-04-12T23:20:40Z |
| format | Article |
| id | doaj.art-a1ec83c9393e4f7eb479d5ceb07e6b9b |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-04-12T23:20:40Z |
| publishDate | 2019-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-a1ec83c9393e4f7eb479d5ceb07e6b9b2022-12-22T03:12:32ZengIEEEIEEE Access2169-35362019-01-01711916611918010.1109/ACCESS.2019.29373848812735A 16-Bit 1-MS/s Pseudo-Differential SAR ADC With Digital Calibration and DNL Enhancement Achieving 92 dB SNDRPanpan Zhang0https://orcid.org/0000-0003-4980-3632Wenjiang Feng1Peng Zhao2Xiaoping Chen3Zongjiang Zhang4College of Microelectronics and Communication Engineering, Chongqing University, Chongqing, ChinaCollege of Microelectronics and Communication Engineering, Chongqing University, Chongqing, ChinaShenzhen State Micro Electronics Company Ltd., Shenzhen, ChinaShenzhen State Micro Electronics Company Ltd., Shenzhen, ChinaShenzhen State Micro Electronics Company Ltd., Shenzhen, ChinaThis paper presents a 16-bit 1 MS/s pseudo-differential Successive-Approximation-Register Analog-to-Digital Converter (SAR ADC) achieving an ENOB of 15-bit. To accommodate the pseudo-differential input, a differential DAC utilizing both monotonic and traditional switching is designed. For both dynamic and static performance improvement, three techniques are proposed. First, a foreground digital self-calibration method is described to eliminate the capacitor mismatch errors. Some of the LSBs capacitors are utilized to measure and calculate the bit weights of other capacitors. Second, a DNL enhancement technique is presented. The fractional value capacitors are used to subtract an analog voltage from the DAC before the conversion is finished, which cancels out the consequent effect when the fractional part of the digital output is discarded before final output. Third, a low-offset low-noise comparator is designed. A reset timer with DAC settling replica is proposed to make the pre-amplifier in the comparator to start to amplify the DAC summing node voltage right after the DAC has fully settled. A prototype ADC is fabricated in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> 5-V CMOS process. It measures a 92.3-dB SNDR and a 107.9-dB SFDR. The DNL and INL are within ±0.3 LSB and ±0.72 LSB, respectively. The overall power consumption, drawn from the 5 V power supply, is 40 mW.https://ieeexplore.ieee.org/document/8812735/Successive-approximation-register analog-to-digital converter (SAR ADC)digital calibrationpseudo-differentialDNL enhancement |
| spellingShingle | Panpan Zhang Wenjiang Feng Peng Zhao Xiaoping Chen Zongjiang Zhang A 16-Bit 1-MS/s Pseudo-Differential SAR ADC With Digital Calibration and DNL Enhancement Achieving 92 dB SNDR IEEE Access Successive-approximation-register analog-to-digital converter (SAR ADC) digital calibration pseudo-differential DNL enhancement |
| title | A 16-Bit 1-MS/s Pseudo-Differential SAR ADC With Digital Calibration and DNL Enhancement Achieving 92 dB SNDR |
| title_full | A 16-Bit 1-MS/s Pseudo-Differential SAR ADC With Digital Calibration and DNL Enhancement Achieving 92 dB SNDR |
| title_fullStr | A 16-Bit 1-MS/s Pseudo-Differential SAR ADC With Digital Calibration and DNL Enhancement Achieving 92 dB SNDR |
| title_full_unstemmed | A 16-Bit 1-MS/s Pseudo-Differential SAR ADC With Digital Calibration and DNL Enhancement Achieving 92 dB SNDR |
| title_short | A 16-Bit 1-MS/s Pseudo-Differential SAR ADC With Digital Calibration and DNL Enhancement Achieving 92 dB SNDR |
| title_sort | 16 bit 1 ms s pseudo differential sar adc with digital calibration and dnl enhancement achieving 92 db sndr |
| topic | Successive-approximation-register analog-to-digital converter (SAR ADC) digital calibration pseudo-differential DNL enhancement |
| url | https://ieeexplore.ieee.org/document/8812735/ |
| work_keys_str_mv | AT panpanzhang a16bit1msspseudodifferentialsaradcwithdigitalcalibrationanddnlenhancementachieving92dbsndr AT wenjiangfeng a16bit1msspseudodifferentialsaradcwithdigitalcalibrationanddnlenhancementachieving92dbsndr AT pengzhao a16bit1msspseudodifferentialsaradcwithdigitalcalibrationanddnlenhancementachieving92dbsndr AT xiaopingchen a16bit1msspseudodifferentialsaradcwithdigitalcalibrationanddnlenhancementachieving92dbsndr AT zongjiangzhang a16bit1msspseudodifferentialsaradcwithdigitalcalibrationanddnlenhancementachieving92dbsndr AT panpanzhang 16bit1msspseudodifferentialsaradcwithdigitalcalibrationanddnlenhancementachieving92dbsndr AT wenjiangfeng 16bit1msspseudodifferentialsaradcwithdigitalcalibrationanddnlenhancementachieving92dbsndr AT pengzhao 16bit1msspseudodifferentialsaradcwithdigitalcalibrationanddnlenhancementachieving92dbsndr AT xiaopingchen 16bit1msspseudodifferentialsaradcwithdigitalcalibrationanddnlenhancementachieving92dbsndr AT zongjiangzhang 16bit1msspseudodifferentialsaradcwithdigitalcalibrationanddnlenhancementachieving92dbsndr |