Impact of Stress and Dimension on Nanosheet Deformation during Channel Release of Gate-All-Around Device

Impact of Stress and Dimension on Nanosheet Deformation during Channel Release of Gate-All-Around Device

In this paper, nanosheet deformation during channel release has been investigated and discussed in Gate-All-Around (GAA) transistors. Structures with different source/drain size and stacked Si nanosheet lengths were designed and fabricated. The experiment of channel release showed that the stress ca...

Full description

Bibliographic Details
Main Authors:	Jingwen Yang, Kun Chen, Dawei Wang, Tao Liu, Xin Sun, Qiang Wang, Ziqiang Huang, Zhecheng Pan, Saisheng Xu, Chen Wang, Chunlei Wu, Min Xu, David Wei Zhang
Format:	Article
Language:	English
Published:	MDPI AG 2023-03-01
Series:	Micromachines
Subjects:	Gate-All-Around (GAA) stress nanosheet length channel release nanosheet deformation
Online Access:	https://www.mdpi.com/2072-666X/14/3/611

Similar Items

Source/Drain Trimming Process to Improve Gate-All-Around Nanosheet Transistors Switching Performance and Enable More Stacks of Nanosheets
by: Kun Chen, et al.
Published: (2022-07-01)

Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices
by: Qingzhu Zhang, et al.
Published: (2021-03-01)

A Novel Si Nanosheet Channel Release Process for the Fabrication of Gate-All-Around Transistors and Its Mechanism Investigation
by: Xin Sun, et al.
Published: (2023-01-01)

A Vertically Stacked Nanosheet Gate-All-Around FET for Biosensing Application
by: Cong Li, et al.
Published: (2021-01-01)

A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors
by: Jingwen Yang, et al.
Published: (2023-05-01)

A Review of Reliability in Gate-All-Around Nanosheet Devices
by: Miaomiao Wang
Published: (2024-02-01)

Fabrication and Characterization of Stacked Poly-Si Nanosheet With Gate-All-Around and Multi-Gate Junctionless Field Effect Transistors
by: Meng-Ju Tsai, et al.
Published: (2019-01-01)

<i>L<sub>g</sub></i> = 50 nm Gate-All-Around In<i><sub>0.53</sub></i>Ga<i><sub>0.47</sub></i>As Nanosheet MOSFETs with Regrown In<i><sub>0.53</sub></i>Ga<i><sub>0.47</sub></i>As Contacts
by: In-Geun Lee, et al.
Published: (2022-08-01)

Compact Modeling of Advanced Gate-All-Around Nanosheet FETs Using Artificial Neural Network
by: Yage Zhao, et al.
Published: (2024-01-01)

A non-destructive channel stress characterization for gate-all-around nanosheet transistors by confocal Raman methodology
by: Huang Ziqiang, et al.
Published: (2022-09-01)

Strained Si Nanosheet pFET Based on SiC Strain Relaxed Buffer Layer for High Performance and Low Power Logic Applications
by: Kun Chen, et al.
Published: (2023-01-01)

Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors
by: Junjie Li, et al.
Published: (2020-04-01)

Investigation of Source/Drain Recess Engineering and Its Impacts on FinFET and GAA Nanosheet FET at 5 nm Node
by: Dawei Wang, et al.
Published: (2023-02-01)

Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes
by: E. Mohapatra, et al.
Published: (2021-04-01)

Effect of Non-Ideal Cross-Sectional Shape on the Performance of Nanosheet-Based FETs
by: Fengyu Kuang, et al.
Published: (2023-08-01)

Investigation of Electro-Thermal Performance for TreeFET from the Perspective of Structure Parameters
by: Weijing Liu, et al.
Published: (2023-03-01)

Low-Voltage Programmable Gate-All-Around (GAA) Nanosheet TFT Nonvolatile Memory Using Band-to-Band Tunneling Induced Hot Electron (BBHE) Method
by: Lun-Chun Chen, et al.
Published: (2019-01-01)

Design of GAA Nanosheet Ferroelectric Area Tunneling FET and Its Significance with DC/RF Characteristics Including Linearity Analyses
by: Narasimhulu Thoti, et al.
Published: (2022-05-01)

A Review of the Gate-All-Around Nanosheet FET Process Opportunities
by: Sagarika Mukesh, et al.
Published: (2022-11-01)

BSIM-CMG compact model for IC CAD: from FinFET to Gate-All-Around FET Technology
by: Avirup Dasgupta, et al.
Published: (2020-12-01)

A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator
by: Yannan Zhang, et al.
Published: (2020-02-01)

Analytical Current–Voltage Modeling and Analysis of the MFIS Gate-All-Around Transistor Featuring Negative-Capacitance
by: Yeji Kim, et al.
Published: (2021-05-01)

TID Circuit Simulation in Nanowire FETs and Nanosheet FETs
by: Jongwon Lee, et al.
Published: (2021-04-01)

Analytical model of subthreshold swing in junctionless gate-all-around (GAA) FET with ferroelectric
by: Hakkee Jung
Published: (2023-10-01)

A Simulation Study of Gate-All-Around Nanowire Transistor With a Core-Substrate
by: Ke Han, et al.
Published: (2020-01-01)

4-Levels Vertically Stacked SiGe Channel Nanowires Gate-All-Around Transistor with Novel Channel Releasing and Source and Drain Silicide Process
by: Xiaohong Cheng, et al.
Published: (2022-03-01)

Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates
by: Tung-Yu Liu, et al.
Published: (2015-01-01)

N-Type Nanosheet FETs without Ground Plane Region for Process Simplification
by: Khwang-Sun Lee, et al.
Published: (2022-03-01)

Gate-all-around n-MOSFETs with uniaxial tensile strain-induced performance enhancement scalable to sub-10-nm nanowire diameter
by: Gomez, Leonardo, et al.
Published: (2010)

The Artificial Neuron: Built From Nanosheet Transistors to Achieve Ultra Low Power Consumption
by: I. Munavar Sheriff, et al.
Published: (2024-01-01)

Power Reduction in Punch-Through Current-Based Electro-Thermal Annealing in Gate-All-Around FETs
by: Min-Kyeong Kim, et al.
Published: (2022-01-01)

Electrical Characteristic and Power Fluctuations of GAA Si NS CFETs by Simultaneously Considering Six Process Variation Factors
by: Sekhar Reddy Kola, et al.
Published: (2023-01-01)

EFFECT OF PROCESS PARAMETER VARIATION ON ft IN CONVENTIONAL AND JUNCTIONLESS GATE-ALL-AROUND DEVICES
by: B. LAKSHMI, et al.
Published: (2015-08-01)

Mini Review: Nanosheet Technology towards Biomedical Application
by: Sheng Zhang, et al.
Published: (2017-08-01)

A Comprehensive Technique Based on Machine Learning for Device and Circuit Modeling of Gate-All-Around Nanosheet Transistors
by: Rajat Butola, et al.
Published: (2023-01-01)

The Green Synthesis of 2D Copper Nanosheets and Their Light Absorption
by: Suhyun Lee, et al.
Published: (2021-04-01)

Noise Spectroscopy Analysis of Ion Behavior in Liquid Gate‐All‐Around Silicon Nanowire Field‐Effect Transistor Biosensors
by: Yongqiang Zhang, et al.
Published: (2023-12-01)

FinFET to GAA MBCFET: A Review and Insights
by: Rinku Rani Das, et al.
Published: (2024-01-01)

Analysis of Drain-Induced Barrier Lowering for Gate-All-Around FET with Ferroelectric
by: Hakkee Jung
Published: (2024-03-01)

Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs
by: Jie Gu, et al.
Published: (2021-01-01)