A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT Applications

A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT Applications

This paper presents analyses of jitter and reference spur of a digital PLL using a phase-frequency detector (PFD) and a time amplifier (TA). In the PFD-TA PLL, the TA amplifies a phase error between a reference clock and a divided feedback clock. The amplified pulse signals modulate the digitally co...

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Bibliographic Details
Main Authors: Minuk Heo, Sunghyun Bae, Ja-Yol Lee, Cheonsu Kim, Minjae Lee
Format: Article
Language:English
Published: IEEE 2022-01-01
Series:IEEE Access
Subjects:
Time amplifier (TA)
digitally controlled oscillator (DCO)
digital phase-locked loop (PLL)
PLL jitter analysis
reference spur
phase interpolator (PI) nonlinearity calibration
Online Access:https://ieeexplore.ieee.org/document/9794638/

Internet

https://ieeexplore.ieee.org/document/9794638/

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