A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT Applications
This paper presents analyses of jitter and reference spur of a digital PLL using a phase-frequency detector (PFD) and a time amplifier (TA). In the PFD-TA PLL, the TA amplifies a phase error between a reference clock and a divided feedback clock. The amplified pulse signals modulate the digitally co...
| Main Authors: | , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
IEEE
2022-01-01
|
| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9794638/ |
| _version_ | 1811332166555009024 |
|---|---|
| author | Minuk Heo Sunghyun Bae Ja-Yol Lee Cheonsu Kim Minjae Lee |
| author_facet | Minuk Heo Sunghyun Bae Ja-Yol Lee Cheonsu Kim Minjae Lee |
| author_sort | Minuk Heo |
| collection | DOAJ |
| description | This paper presents analyses of jitter and reference spur of a digital PLL using a phase-frequency detector (PFD) and a time amplifier (TA). In the PFD-TA PLL, the TA amplifies a phase error between a reference clock and a divided feedback clock. The amplified pulse signals modulate the digitally controlled oscillator (DCO) frequency. The TA input-referred jitter limits the minimum PFD-TA PLL output jitter in case of the low DCO and reference clock jitter. However, the PFD-TA PLL achieves a lower output jitter than the BBPLL especially when the input noise is worsened by the poor DCO, which, indeed, is common in low-power and IoT applications for lower cost and power. The reference spur caused by the path mismatches of the proposed DCO modulation is analyzed by Fourier Series, and implementing the high-gain (>100) TA reduces the reference spur with the smaller DCO modulating signal distortion. To assist the narrow input dynamic range (< 30ps) of the TA, a 7-bit phase interpolator (PI) is implemented to fractional frequency divider with a PI nonlinearity calibration. The theoretical predictions are compared with the behavioral simulations and verified in measurements where the chip is fabricated in a 40 nm CMOS process, and the PFD-TA PLL consumes 5 mW from a 1.1 V supply. |
| first_indexed | 2024-04-13T16:32:40Z |
| format | Article |
| id | doaj.art-a3647326de974759ae0af81d42c9696a |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-04-13T16:32:40Z |
| publishDate | 2022-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-a3647326de974759ae0af81d42c9696a2022-12-22T02:39:32ZengIEEEIEEE Access2169-35362022-01-0110624716248310.1109/ACCESS.2022.31824859794638A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT ApplicationsMinuk Heo0Sunghyun Bae1Ja-Yol Lee2https://orcid.org/0000-0001-8834-8527Cheonsu Kim3Minjae Lee4https://orcid.org/0000-0003-1500-1404School of Electrical Engineering and Computer Science, Gwangju Institute of Science and Technology, Buk-gu, Gwangju, South KoreaSchool of Electrical Engineering and Computer Science, Gwangju Institute of Science and Technology, Buk-gu, Gwangju, South KoreaElectronics and Telecommunications Research Institute, Yuseong-gu, Daejeon, South KoreaElectronics and Telecommunications Research Institute, Yuseong-gu, Daejeon, South KoreaSchool of Electrical Engineering and Computer Science, Gwangju Institute of Science and Technology, Buk-gu, Gwangju, South KoreaThis paper presents analyses of jitter and reference spur of a digital PLL using a phase-frequency detector (PFD) and a time amplifier (TA). In the PFD-TA PLL, the TA amplifies a phase error between a reference clock and a divided feedback clock. The amplified pulse signals modulate the digitally controlled oscillator (DCO) frequency. The TA input-referred jitter limits the minimum PFD-TA PLL output jitter in case of the low DCO and reference clock jitter. However, the PFD-TA PLL achieves a lower output jitter than the BBPLL especially when the input noise is worsened by the poor DCO, which, indeed, is common in low-power and IoT applications for lower cost and power. The reference spur caused by the path mismatches of the proposed DCO modulation is analyzed by Fourier Series, and implementing the high-gain (>100) TA reduces the reference spur with the smaller DCO modulating signal distortion. To assist the narrow input dynamic range (< 30ps) of the TA, a 7-bit phase interpolator (PI) is implemented to fractional frequency divider with a PI nonlinearity calibration. The theoretical predictions are compared with the behavioral simulations and verified in measurements where the chip is fabricated in a 40 nm CMOS process, and the PFD-TA PLL consumes 5 mW from a 1.1 V supply.https://ieeexplore.ieee.org/document/9794638/Time amplifier (TA)digitally controlled oscillator (DCO)digital phase-locked loop (PLL)PLL jitter analysisreference spurphase interpolator (PI) nonlinearity calibration |
| spellingShingle | Minuk Heo Sunghyun Bae Ja-Yol Lee Cheonsu Kim Minjae Lee A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT Applications IEEE Access Time amplifier (TA) digitally controlled oscillator (DCO) digital phase-locked loop (PLL) PLL jitter analysis reference spur phase interpolator (PI) nonlinearity calibration |
| title | A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT Applications |
| title_full | A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT Applications |
| title_fullStr | A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT Applications |
| title_full_unstemmed | A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT Applications |
| title_short | A 3-3.7GHz Time-Difference Controlled Digital Fractional-N PLL With a High-Gain Time Amplifier for IoT Applications |
| title_sort | 3 3 7ghz time difference controlled digital fractional n pll with a high gain time amplifier for iot applications |
| topic | Time amplifier (TA) digitally controlled oscillator (DCO) digital phase-locked loop (PLL) PLL jitter analysis reference spur phase interpolator (PI) nonlinearity calibration |
| url | https://ieeexplore.ieee.org/document/9794638/ |
| work_keys_str_mv | AT minukheo a337ghztimedifferencecontrolleddigitalfractionalnpllwithahighgaintimeamplifierforiotapplications AT sunghyunbae a337ghztimedifferencecontrolleddigitalfractionalnpllwithahighgaintimeamplifierforiotapplications AT jayollee a337ghztimedifferencecontrolleddigitalfractionalnpllwithahighgaintimeamplifierforiotapplications AT cheonsukim a337ghztimedifferencecontrolleddigitalfractionalnpllwithahighgaintimeamplifierforiotapplications AT minjaelee a337ghztimedifferencecontrolleddigitalfractionalnpllwithahighgaintimeamplifierforiotapplications AT minukheo 337ghztimedifferencecontrolleddigitalfractionalnpllwithahighgaintimeamplifierforiotapplications AT sunghyunbae 337ghztimedifferencecontrolleddigitalfractionalnpllwithahighgaintimeamplifierforiotapplications AT jayollee 337ghztimedifferencecontrolleddigitalfractionalnpllwithahighgaintimeamplifierforiotapplications AT cheonsukim 337ghztimedifferencecontrolleddigitalfractionalnpllwithahighgaintimeamplifierforiotapplications AT minjaelee 337ghztimedifferencecontrolleddigitalfractionalnpllwithahighgaintimeamplifierforiotapplications |