A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems

A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems

An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented. The proposed architecture is based on an all-digital multiplying delay-locked loop (MDLL) to provide fast locking time and multiplied output...

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Bibliographic Details
Main Authors: Junghoon Jin, Seungjun Kim, Jongsun Kim
Format: Article
Language:English
Published: IEEE 2022-01-01
Series:IEEE Access
Subjects:
MDLL
multiplying delay-locked loop
clock generator
time-to-digital converter
TDC
digitally-controlled oscillator
Online Access:https://ieeexplore.ieee.org/document/9963564/

Internet

https://ieeexplore.ieee.org/document/9963564/

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