A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems
An all-digital clock frequency multiplier that achieves excellent locking time for an energy-efficient chiplet-based system-on-chip (SoC) design is presented. The proposed architecture is based on an all-digital multiplying delay-locked loop (MDLL) to provide fast locking time and multiplied output...
Main Authors: | Junghoon Jin, Seungjun Kim, Jongsun Kim |
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Format: | Article |
Language: | English |
Published: |
IEEE
2022-01-01
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Series: | IEEE Access |
Subjects: | |
Online Access: | https://ieeexplore.ieee.org/document/9963564/ |
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