Source Design of Vertical III–V Nanowire Tunnel Field-Effect Transistors
We systematically fabricate devices and analyze data for vertical InAs/(In)GaAsSb nanowire tunnel field-effect transistors (TFETs), to study the influence of source dopant position and level on their device performance. The results show that delaying the introduction of dopants further in the GaAsSb...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2024-01-01
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| Series: | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10409158/ |