A Sparse Neural Network-Based Power Adaptive DPD Design and Its Hardware Implementation

A Sparse Neural Network-Based Power Adaptive DPD Design and Its Hardware Implementation

In this paper, an efficient neural-network-based adaptive DPD design which performs well under power varying conditions is presented. The DPD design is derived on the basis of the envelop time-delay neural network (ETDNN). The redefined ETDNN-DPD requires the part of parameter updates, which enables...

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Bibliographic Details
Main Authors: Masaaki Tanio, Naoto Ishii, Norifumi Kamiya
Format: Article
Language:English
Published: IEEE 2022-01-01
Series:IEEE Access
Subjects:
Digital predistortion
memory polynomial
FPGA implementation
neural network
pruning technique
physical model
Online Access:https://ieeexplore.ieee.org/document/9932585/

Internet

https://ieeexplore.ieee.org/document/9932585/

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