A system-level method for hardening phase-locked loop to single-event effects
To mitigate the sensitivity of the charge pump in a traditional Phase-Locked Loop(PLL), a single-event-hardened PLL architecture with a proportional and integral path is proposed. The phase margin of the PLL is kept at 58.16° due to the rational design and the output clock frequency ranges from 0.8...
| Main Authors: | , , , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
IOP Publishing
2022-01-01
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| Series: | Materials Research Express |
| Subjects: | |
| Online Access: | https://doi.org/10.1088/2053-1591/ac8f87 |