On the Positional Single Error Correction and Double Error Detection in Racetrack Memories
In the era of non-volatile memories, the racetrack memory is a promising technology to pack hundreds of bits in a magnetic nanowire. A solid-state read head is grown alongside the nanowire to sense individual bits which are pushed across the head by a shifting force. However, the probabilistic natur...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2023-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/10050207/ |
| _version_ | 1811162826297835520 |
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| author | Awais Saeed Ubaid U. Fayyaz Ahsan Tahir Seokin Hong Tayyeb Mahmood |
| author_facet | Awais Saeed Ubaid U. Fayyaz Ahsan Tahir Seokin Hong Tayyeb Mahmood |
| author_sort | Awais Saeed |
| collection | DOAJ |
| description | In the era of non-volatile memories, the racetrack memory is a promising technology to pack hundreds of bits in a magnetic nanowire. A solid-state read head is grown alongside the nanowire to sense individual bits which are pushed across the head by a shifting force. However, the probabilistic nature of this shifting movement inflicts positional errors. Therefore, robust and low-cost error correcting codes are essential for a reliable alternative in on-chip memories and storage applications. Recent works focus on Varshamov-Tenengolts (VT) codes which can correct all single bit insertions and deletions. However, VT codes are incapable of detecting multiple deletions/insertions. Because a positional error corrupts multiple data words, multi-bit positional error detection is critical for racetrack memories. In this article, we propose a novel positional single error correction and double error detection (P-SECDED) code in the context of racetrack memories with a single read head. In particular, we adopt a postamble-based approach where a VT-encoded codeword appends a carefully selected bit-pattern, stored on the racetrack. We rigorously analyze the limitations of the postamble method, and deduce a criterion for postamble selection. We further provide a methodology to optimize this postamble selection in order to correct all single-bit errors and as much of two-bit errors as possible. Finally, we prove that all incurable two-bit errors are successfully detected. To the best of our knowledge, this work is the first attempt to provide P-SECDED fault-tolerance to three-dimensional racetrack memories which cannot afford multiple read heads. |
| first_indexed | 2024-04-10T06:36:35Z |
| format | Article |
| id | doaj.art-a7713cffe1814a7f84c2b8bbffb27fea |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-04-10T06:36:35Z |
| publishDate | 2023-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-a7713cffe1814a7f84c2b8bbffb27fea2023-03-01T00:01:06ZengIEEEIEEE Access2169-35362023-01-0111183001831010.1109/ACCESS.2023.324672610050207On the Positional Single Error Correction and Double Error Detection in Racetrack MemoriesAwais Saeed0https://orcid.org/0000-0002-7000-6892Ubaid U. Fayyaz1https://orcid.org/0000-0001-7833-6127Ahsan Tahir2https://orcid.org/0000-0001-8247-9390Seokin Hong3https://orcid.org/0000-0001-7842-125XTayyeb Mahmood4https://orcid.org/0000-0002-8853-305XDepartment of Electrical Engineering, University of Engineering and Technology, Lahore, Lahore, PakistanDepartment of Electrical Engineering, University of Engineering and Technology, Lahore, Lahore, PakistanDepartment of Electrical Engineering, University of Engineering and Technology, Lahore, Lahore, PakistanDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Republic of KoreaDepartment of Electrical Engineering, University of Engineering and Technology, Lahore, Lahore, PakistanIn the era of non-volatile memories, the racetrack memory is a promising technology to pack hundreds of bits in a magnetic nanowire. A solid-state read head is grown alongside the nanowire to sense individual bits which are pushed across the head by a shifting force. However, the probabilistic nature of this shifting movement inflicts positional errors. Therefore, robust and low-cost error correcting codes are essential for a reliable alternative in on-chip memories and storage applications. Recent works focus on Varshamov-Tenengolts (VT) codes which can correct all single bit insertions and deletions. However, VT codes are incapable of detecting multiple deletions/insertions. Because a positional error corrupts multiple data words, multi-bit positional error detection is critical for racetrack memories. In this article, we propose a novel positional single error correction and double error detection (P-SECDED) code in the context of racetrack memories with a single read head. In particular, we adopt a postamble-based approach where a VT-encoded codeword appends a carefully selected bit-pattern, stored on the racetrack. We rigorously analyze the limitations of the postamble method, and deduce a criterion for postamble selection. We further provide a methodology to optimize this postamble selection in order to correct all single-bit errors and as much of two-bit errors as possible. Finally, we prove that all incurable two-bit errors are successfully detected. To the best of our knowledge, this work is the first attempt to provide P-SECDED fault-tolerance to three-dimensional racetrack memories which cannot afford multiple read heads.https://ieeexplore.ieee.org/document/10050207/Magnetic storagesolid-state storageultra-dense storageinsertion deletion channelsdomain-wall memoriesskyrmions memories |
| spellingShingle | Awais Saeed Ubaid U. Fayyaz Ahsan Tahir Seokin Hong Tayyeb Mahmood On the Positional Single Error Correction and Double Error Detection in Racetrack Memories IEEE Access Magnetic storage solid-state storage ultra-dense storage insertion deletion channels domain-wall memories skyrmions memories |
| title | On the Positional Single Error Correction and Double Error Detection in Racetrack Memories |
| title_full | On the Positional Single Error Correction and Double Error Detection in Racetrack Memories |
| title_fullStr | On the Positional Single Error Correction and Double Error Detection in Racetrack Memories |
| title_full_unstemmed | On the Positional Single Error Correction and Double Error Detection in Racetrack Memories |
| title_short | On the Positional Single Error Correction and Double Error Detection in Racetrack Memories |
| title_sort | on the positional single error correction and double error detection in racetrack memories |
| topic | Magnetic storage solid-state storage ultra-dense storage insertion deletion channels domain-wall memories skyrmions memories |
| url | https://ieeexplore.ieee.org/document/10050207/ |
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