Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

Side-channel attacks constitute a concrete threat to IoT systems-on-a-chip (SoCs). Embedded memories implemented with 6T SRAM macrocells often dominate the area and power consumption of these SoCs. Regardless of the computational platform, the side-channel sensitivity of low-hierarchy cache memories...

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Bibliographic Details
Main Authors: Yoav Weizman, Robert Giterman, Oron Chertkow, Maoz Wicentowski, Itamar Levi, Ilan Sever, Ishai Kehati, Osnat Keren, Alexander Fish
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Access
Subjects:
Secured Static Random Access Memories (SRAM)
hardware security
power analysis
secured memory
Online Access:https://ieeexplore.ieee.org/document/9453841/

Internet

https://ieeexplore.ieee.org/document/9453841/

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