Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads
Side-channel attacks constitute a concrete threat to IoT systems-on-a-chip (SoCs). Embedded memories implemented with 6T SRAM macrocells often dominate the area and power consumption of these SoCs. Regardless of the computational platform, the side-channel sensitivity of low-hierarchy cache memories...
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| Format: | Article |
| Language: | English |
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IEEE
2021-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9453841/ |
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| author | Yoav Weizman Robert Giterman Oron Chertkow Maoz Wicentowski Itamar Levi Ilan Sever Ishai Kehati Osnat Keren Alexander Fish |
| author_facet | Yoav Weizman Robert Giterman Oron Chertkow Maoz Wicentowski Itamar Levi Ilan Sever Ishai Kehati Osnat Keren Alexander Fish |
| author_sort | Yoav Weizman |
| collection | DOAJ |
| description | Side-channel attacks constitute a concrete threat to IoT systems-on-a-chip (SoCs). Embedded memories implemented with 6T SRAM macrocells often dominate the area and power consumption of these SoCs. Regardless of the computational platform, the side-channel sensitivity of low-hierarchy cache memories can incur significant overhead to protect the memory content (i.e., data encryption, data masking, etc.). In this manuscript, we provide a silicon proof of the effectiveness of a low cost side-channel attack protection that is embedded within the memory macro to achieve a significant reduction in information leakage. The proposed solution incorporates low-cost impedance randomization units, which are integrated into the periphery of a conventional 6T SRAM macro in fine-grain memory partitions, providing possible protection against electromagnetic adversaries. Various blocks of unprotected and protected SRAM macros were designed and fabricated in a 55 nm test-chip. The protected ones had little as 1% area overhead and less than 5% performance and power penalties compared to a conventional SRAM design. To evaluate the security of the proposed solution, we applied a robust mutual information metric and an adaptation to the memory context to enhance this evaluation framework. Assessment of the protected memory demonstrated a significant information leakage reduction from 8 bits of information exposed after only 100 cycles of attack to less than ~1.5 bits of mutual information after 160K traces. The parametric nature of the protection mechanisms are discussed while specifying the proposed design parameters. Overall, the proposed methodology enables designs with higher security-level at a minimal cost. |
| first_indexed | 2024-12-14T17:08:44Z |
| format | Article |
| id | doaj.art-a77d54e85d7d40a1aa1b6ba68eb06cc6 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-14T17:08:44Z |
| publishDate | 2021-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-a77d54e85d7d40a1aa1b6ba68eb06cc62022-12-21T22:53:39ZengIEEEIEEE Access2169-35362021-01-019917649177610.1109/ACCESS.2021.30889919453841Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power OverheadsYoav Weizman0Robert Giterman1https://orcid.org/0000-0002-1410-4746Oron Chertkow2Maoz Wicentowski3Itamar Levi4https://orcid.org/0000-0002-5591-5799Ilan Sever5Ishai Kehati6Osnat Keren7https://orcid.org/0000-0002-3101-9551Alexander Fish8Faculty of Engineering, Bar-Ilan University, Ramat Gan, IsraelInstitute of Electrical Engineering, École Polytechnique Fédérale de Lausanne (EPFL), Lausanne, SwitzerlandAmdocs, Israel Ltd., Raanana, IsraelSamsung Electronics Israel, Petah Tikva, IsraelFaculty of Engineering, Bar-Ilan University, Ramat Gan, IsraelWeebit Nano, Hod Hasharon, IsraelEthernity Networks, Lod, IsraelFaculty of Engineering, Bar-Ilan University, Ramat Gan, IsraelFaculty of Engineering, Bar-Ilan University, Ramat Gan, IsraelSide-channel attacks constitute a concrete threat to IoT systems-on-a-chip (SoCs). Embedded memories implemented with 6T SRAM macrocells often dominate the area and power consumption of these SoCs. Regardless of the computational platform, the side-channel sensitivity of low-hierarchy cache memories can incur significant overhead to protect the memory content (i.e., data encryption, data masking, etc.). In this manuscript, we provide a silicon proof of the effectiveness of a low cost side-channel attack protection that is embedded within the memory macro to achieve a significant reduction in information leakage. The proposed solution incorporates low-cost impedance randomization units, which are integrated into the periphery of a conventional 6T SRAM macro in fine-grain memory partitions, providing possible protection against electromagnetic adversaries. Various blocks of unprotected and protected SRAM macros were designed and fabricated in a 55 nm test-chip. The protected ones had little as 1% area overhead and less than 5% performance and power penalties compared to a conventional SRAM design. To evaluate the security of the proposed solution, we applied a robust mutual information metric and an adaptation to the memory context to enhance this evaluation framework. Assessment of the protected memory demonstrated a significant information leakage reduction from 8 bits of information exposed after only 100 cycles of attack to less than ~1.5 bits of mutual information after 160K traces. The parametric nature of the protection mechanisms are discussed while specifying the proposed design parameters. Overall, the proposed methodology enables designs with higher security-level at a minimal cost.https://ieeexplore.ieee.org/document/9453841/Secured Static Random Access Memories (SRAM)hardware securitypower analysissecured memory |
| spellingShingle | Yoav Weizman Robert Giterman Oron Chertkow Maoz Wicentowski Itamar Levi Ilan Sever Ishai Kehati Osnat Keren Alexander Fish Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads IEEE Access Secured Static Random Access Memories (SRAM) hardware security power analysis secured memory |
| title | Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads |
| title_full | Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads |
| title_fullStr | Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads |
| title_full_unstemmed | Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads |
| title_short | Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads |
| title_sort | low cost side channel secure standard 6t sram based memory with a 1 x0025 area and less than 5 x0025 latency and power overheads |
| topic | Secured Static Random Access Memories (SRAM) hardware security power analysis secured memory |
| url | https://ieeexplore.ieee.org/document/9453841/ |
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