Formalizing Memory Accesses and Interrupts
The hardware/software boundary in modern heterogeneous multicore computers is increasingly complex, and diverse across different platforms. A single memory access by a core or DMA engine traverses multiple hardware translation and caching steps, and the destination memory cell or register often appe...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Open Publishing Association
2017-03-01
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| Series: | Electronic Proceedings in Theoretical Computer Science |
| Online Access: | http://arxiv.org/pdf/1703.06571v1 |