Longest Path Selection Based on Path Identifiers
A small delay defect adds a small extra delay to the propagation time of a signal through a gate or line. Small delay defects can occur during fabrication or during the lifetime of a chip. When a path with small delay defects has a delay that exceeds its permissible value based on the clock period,...
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| Format: | Article |
| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10412039/ |
| _version_ | 1797335525294604288 |
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| author | Irith Pomeranz |
| author_facet | Irith Pomeranz |
| author_sort | Irith Pomeranz |
| collection | DOAJ |
| description | A small delay defect adds a small extra delay to the propagation time of a signal through a gate or line. Small delay defects can occur during fabrication or during the lifetime of a chip. When a path with small delay defects has a delay that exceeds its permissible value based on the clock period, timing failures may occur. To detect small delay defects, test generation procedures target path delay faults that are associated with the longest paths. Storage of paths can have a significant memory overhead. To avoid this overhead, it was shown earlier that paths can be associated with unique integer identifiers. The identifiers are based on a labeling of the circuit lines with two integer labels that are computed in linear time. This article suggests a third integer label, also computed in linear time, that allows a subset of the longest paths to be identified based only on their integer identifiers. The third label ensures that the longest path has identifier 0, and shorter paths have larger identifiers. Thus, with an exception discussed and addressed in the article, it is possible to target the longest paths for test generation by targeting the paths with identifiers 0, 1, 2, <inline-formula> <tex-math notation="LaTeX">$\ldots $ </tex-math></inline-formula>. An identifier needs to be translated into a physical path only when it is targeted for test generation. The article applies the new labeling to benchmark circuits and presents experimental results to demonstrate its effectiveness. |
| first_indexed | 2024-03-08T08:39:34Z |
| format | Article |
| id | doaj.art-a90576fc6c87454aaad256abd3960b35 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-03-08T08:39:34Z |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-a90576fc6c87454aaad256abd3960b352024-02-02T00:04:19ZengIEEEIEEE Access2169-35362024-01-0112145121452010.1109/ACCESS.2024.335775410412039Longest Path Selection Based on Path IdentifiersIrith Pomeranz0https://orcid.org/0000-0002-5491-7282School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USAA small delay defect adds a small extra delay to the propagation time of a signal through a gate or line. Small delay defects can occur during fabrication or during the lifetime of a chip. When a path with small delay defects has a delay that exceeds its permissible value based on the clock period, timing failures may occur. To detect small delay defects, test generation procedures target path delay faults that are associated with the longest paths. Storage of paths can have a significant memory overhead. To avoid this overhead, it was shown earlier that paths can be associated with unique integer identifiers. The identifiers are based on a labeling of the circuit lines with two integer labels that are computed in linear time. This article suggests a third integer label, also computed in linear time, that allows a subset of the longest paths to be identified based only on their integer identifiers. The third label ensures that the longest path has identifier 0, and shorter paths have larger identifiers. Thus, with an exception discussed and addressed in the article, it is possible to target the longest paths for test generation by targeting the paths with identifiers 0, 1, 2, <inline-formula> <tex-math notation="LaTeX">$\ldots $ </tex-math></inline-formula>. An identifier needs to be translated into a physical path only when it is targeted for test generation. The article applies the new labeling to benchmark circuits and presents experimental results to demonstrate its effectiveness.https://ieeexplore.ieee.org/document/10412039/Launch-on-capture testslaunch-on-shift testspath delay faultspath selectiontest generation |
| spellingShingle | Irith Pomeranz Longest Path Selection Based on Path Identifiers IEEE Access Launch-on-capture tests launch-on-shift tests path delay faults path selection test generation |
| title | Longest Path Selection Based on Path Identifiers |
| title_full | Longest Path Selection Based on Path Identifiers |
| title_fullStr | Longest Path Selection Based on Path Identifiers |
| title_full_unstemmed | Longest Path Selection Based on Path Identifiers |
| title_short | Longest Path Selection Based on Path Identifiers |
| title_sort | longest path selection based on path identifiers |
| topic | Launch-on-capture tests launch-on-shift tests path delay faults path selection test generation |
| url | https://ieeexplore.ieee.org/document/10412039/ |
| work_keys_str_mv | AT irithpomeranz longestpathselectionbasedonpathidentifiers |