A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage

A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage

Abstract The preamplifier module is a crucial element while designing dynamic latch comparators. The traditional double tail comparator utilizes a differential pair as the preamplifier stage. The circuit is generally suffered from high power dissipation and low comparison speed. This research report...

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Bibliographic Details
Main Authors: Jérôme K. Folla, Maria L. Crespo, Evariste T. Wembe, Mohammad A. S. Bhuiyan, Andres Cicuttin, Bernard Z. Essimbi, Mamun B. I. Reaz
Format: Article
Language:English
Published: Hindawi-IET 2021-01-01
Series:IET Circuits, Devices and Systems
Subjects:
clocks
CMOS logic circuits
comparators (circuits)
flip‐flops
high‐speed integrated circuits
integrated circuit layout
Online Access:https://doi.org/10.1049/cds2.12008

Internet

https://doi.org/10.1049/cds2.12008

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