Application of Generative Adversarial Networks for Virtual Silicon Data Generation and Design-Technology Co-Optimization: A Study on WAT and CP

Application of Generative Adversarial Networks for Virtual Silicon Data Generation and Design-Technology Co-Optimization: A Study on WAT and CP

This study explores the application of Generative Adversarial Networks (GANs) for generating wafer-level Wafer Acceptance Test (WAT) and Chip Probe (CP) test data in chip manufacturing processes, with a focus on Design-Technology Co-Optimization (DTCO). The generated virtual silicon data encompasses...

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Bibliographic Details
Main Authors: Shih-Nung Chen, Shi-Hao Chen
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Access
Subjects:
Generative adversarial network (GAN)
wafer acceptance test (WAT)
chip probe (CP)
design-technology co-optimization (DTCO)
virtual silicon data
electronic design automation (EDA)
Online Access:https://ieeexplore.ieee.org/document/10385041/

Internet

https://ieeexplore.ieee.org/document/10385041/

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