Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs

Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs

This paper presents the design of a low-latency, highly linear current-steering DAC for use in continuous-time ADCs. A detailed analysis of equivalent unary-weighted current-steering DAC topologies in terms of mismatch, noise, and output-impedance related distortion is carried out. From this analysi...

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Bibliographic Details
Main Authors: Shantanu Mehta, Daniel O'Hare, Vincent O'Brien, Eric Thompson, Brendan Mullane
Format: Article
Language:English
Published: IEEE 2020-01-01
Series:IEEE Open Journal of Circuits and Systems
Subjects:
Tri-level
current-steering
DACs
thermal noise
DNL
INL
Online Access:https://ieeexplore.ieee.org/document/9094170/

Internet

https://ieeexplore.ieee.org/document/9094170/

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